[Front cover]

Conference Information (PDF)

pp. x-xiv

[Copyright notice] (PDF)

pp. iv

Table of contents (PDF)

pp. v-ix

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

Overview of the Scalable Communications Core: A Reconfigurable Wireless Baseband in 65nm CMOS (Abstract)

Anthony Chun

Kyle McCanta

Edgar Borrayo Sandoval

Kapil Gulati

pp. 1-6

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Chandrasekaran Srinivasaraman

Reduction of Current Mismatch in PLL Charge Pump (Abstract)

H. Md. Shuaeb Fazeel

Leneesh Raghavan

Manish Jain

pp. 7-12

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Low Phase-Noise and Wide Tuning-Range CMOS Differential VCO for Frequency ?S Modulator (Abstract)

pp. 13-18

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A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip (Abstract)

pp. 19-24

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High Performance Non-blocking Switch Design in 3D Die-Stacking Technology (Abstract)

Dean L. Lewis

Sudhakar Yalamanchili

Hsien-Hsin S. Lee

pp. 25-30

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Leakage Power and Side Channel Security of Nanoscale Cryptosystem-on-Chip (CoC) (Abstract)

Amir Khatib Zadeh

Catherine Gebotys

pp. 31-36

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Context-aware Post Routing Redundant Via Insertion (Abstract)

pp. 37-42

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Efficient Rerouting Algorithms for Congestion Mitigation (Abstract)

M.A.R. Chaudhry

Z. Asad

A. Sprintson

J. Hu

pp. 43-48

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A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient (Abstract)

Venkateswaran Nagarajan

Ravindhiran Mukundrajan

Mrigank Sharma

Badrinarayanan Ravi

pp. 49-54

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On-the-Fly Evaluation of FPGA-Based True Random Number Generator (Abstract)

pp. 55-60

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Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs (Abstract)

Prasanth Mangalagiri

Vijaykrishnan Narayanan

pp. 61-66

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A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching (Abstract)

Jian Huang

Jooheung Lee

pp. 67-72

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Vijaya Sankara Rao Pasupureddi

High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect (Abstract)

Pradip Mandal

Sunil Sachdev

pp. 73-78

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Modern Floorplanning with Boundary Clustering Constraint (Abstract)

Li Li

Yuchun Ma

Ning Xu

Yu Wang

Xianlong Hong

pp. 79-84

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An Efficient Hardware Architecture for Multimedia Encryption and Authentication Using the Discrete Wavelet Transform (Abstract)

Amit Pande

Joseph Zambreno

pp. 85-90

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A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits (Abstract)

Koustav Bhattacharya

Nagarajan Ranganathan

pp. 91-96

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Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation (Abstract)

pp. 97-102

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Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication (Abstract)

pp. 103-108

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On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise (Abstract)

Yan Xu

Yu Wang

pp. 109-114

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Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding (Abstract)

pp. 115-120

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Dual-Sum Single-Carry Self-Timed Adder Designs (Abstract)

P. Balasubramanian

D.A. Edwards

pp. 121-126

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Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations (Abstract)

Jins D. Alexander

Vishwani D. Agrawal

pp. 127-132

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Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits (Abstract)

pp. 133-138

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Testing Circuit-Partitioned 3D IC Designs (Abstract)

Dean L. Lewis

Hsien-Hsin S. Lee

pp. 139-144

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Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems (Abstract)

Weixun Wang

Prabhat Mishra

pp. 145-150

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Scheduling for an Embedded Architecture with a Flexible Datapath (Abstract)

pp. 151-156

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Mapping Data and Code into Scratchpads from Relocatable Binaries (Abstract)

Alexandre K.I. Mendonca

pp. 157-162

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Lossless Compression Using Efficient Encoding of Bitmasks (Abstract)

Chetan Murthy

Prabhat Mishra

pp. 163-168

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Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design (Abstract)

Debasri Saha

Susmita Sur-Kolay

pp. 169-174

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Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs (Abstract)

pp. 175-180

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An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor (Abstract)

pp. 181-186

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Inducing Thermal-Awareness in Multicore Systems Using Networks-on-Chip (Abstract)

David Atienza

Emilio Martinez

pp. 187-192

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A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications (Abstract)

Sungmin Bae

Ramakrishnan Krishnan

Vijaykrishnan Narayanan

pp. 193-198

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High Speed Parallel Architecture for Cyclic Convolution Based on FNT (Abstract)

Jian Zhang

Shuguo Li

pp. 199-204

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A High-Speed GCD Chip: A Case Study in Asynchronous Design (Abstract)

pp. 205-210

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A High Performance Unified BCD and Binary Adder/Subtractor (Abstract)

Anshul Singh

Aman Gupta

Sreehari Veeramachaneni

M.B. Srinivas

pp. 211-216

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[Publisher's information] (PDF)

pp. 314

Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration (Abstract)

Hai Li

pp. 217-222

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The Ternary Quantum-dot Cellular Automata Memorizing Cell (Abstract)

pp. 223-228

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Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate (Abstract)

Himanshu Thapliyal

Nagarajan Ranganathan

pp. 229-234

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NoC Power Optimization Using a Reconfigurable Router (Abstract)

pp. 235-240

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Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models (Abstract)

Di Wang

Wei Qin

pp. 241-246

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Power-Efficient Body-Coupled Self-Cascode LC Oscillator for Low-Power Injection-Locked Transmitter Applications (Abstract)

Mohammad Rafiqul Haider

Syed Kamrul Islam

pp. 247-251

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Energy-Efficient Encoding for High-Performance Buses with Staggered Repeaters (Abstract)

Sharath Jayaprakash

Nihar R. Mahapatra

pp. 252-257

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All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex (Abstract)

Swathi Ramasahayam

M.B. Srinivas

pp. 258-262

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A Process Variation Tolerant Self-Compensating Sense Amplifier Design (Abstract)

Aarti Choudhary

Sandip Kundu

pp. 263-267

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An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC (Abstract)

Santanu Sarkar

Swapna Banerjee

pp. 268-273

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Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs (Abstract)

Hariharan Sankaran

Srinivas Katkoori

pp. 274-279

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Low Cost and Memoryless CAVLD Architecture for H.264/AVC Decoder (Abstract)

Thaísa Leal da Silva

João Alberto Vortmann

Luciano Volcan Agostini

Altamiro Amadeu Susin

Sergio Bampi

pp. 280-285

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TEPS: Transient Error Protection Utilizing Sub-word Parallelism (Abstract)

Seokin Hong

Soontae Kim

pp. 286-291

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A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future Technologies (Abstract)

Eduardo Luis Rhod

Luigi Carro

pp. 292-297

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Variation Aware Routing for Three-Dimensional FPGAs (Abstract)

pp. 298-303

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Increasing the Sensitivity of On-Chip Digital Thermal Sensors with Pre-Filtering (Abstract)

pp. 304-309

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Author Index (PDF)

pp. 310-312