Message from the Chairs

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HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems (Abstract)

Nicolas Saint-Jean, LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France

Gilles Sassatelli, LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France

Pascal Benoit, LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France

Lionel Torres, LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France

Michel Robert, LIRMM, UMR 5506, University of Montpellier 2-CNRS, 161 rue Ada, 34392 Montpellier Cedex 5, France

pp. 21-28

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Technological hybridization for efficient runtime reconfigurable FPGAs (Abstract)

N. Bruchon, University of Montpellier 2, Montpellier Cedex 5, France

L. Torres, University of Montpellier 2, Montpellier Cedex 5, France

G. Sassatelli, University of Montpellier 2, Montpellier Cedex 5, France

G. Cambon, University of Montpellier 2, Montpellier Cedex 5, France

pp. 29-34

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Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC (Abstract)

Alisson V. Brito, Universitaet Karlsruhe (TH), Germany

Matthias Kuhnle, Universitaet Karlsruhe (TH), Germany

Michael Hubner, Universitaet Karlsruhe (TH), Germany

Jurgen Becker, Universitaet Karlsruhe (TH), Germany

Elmar U. K. Melcher, Universitaet Karlsruhe (TH), Germany

pp. 35-40

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Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs (Abstract)

Michael Hubner, Universitat Karlsruhe (TH), Germany

Lars Braun, Universitat Karlsruhe (TH), Germany

Jurgen Becker, Universitat Karlsruhe (TH), Germany

Christopher Claus, Munich University of Technology

Walter Stechele, Munich University of Technology

pp. 41-46

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A Polynomial Placement Algorithm for Data Driven Coarse-Grained Reconfigurable Architectures (Abstract)

Ricardo Ferreira, Universidade Federal de Vicosa, Brazil

Alisson Garcia, Universidade Federal de Vicosa, Brazil

Tiago Teixeira, Universidade Federal de Vicosa, Brazil

Joao M. P. Cardoso, INESC-ID/IST/UTL, Portugal

pp. 61-66

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3D-Vias Aware Quadratic Placement for 3D VLSI Circuits (Abstract)

Renato Hentschke, UFRGS - Universidade Federal do Rio Grande do Sul, Brazil

Guilherme Flach, UFRGS - Universidade Federal do Rio Grande do Sul, Brazil

Felipe Pinto, UFRGS - Universidade Federal do Rio Grande do Sul, Brazil

Ricardo Reis, UFRGS - Universidade Federal do Rio Grande do Sul, Brazil

pp. 67-72

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Minimum-Congestion Placement for Y-interconnects: Some studies and observations (Abstract)

Tuhina Samanta, Bengal Engineering & Science University, Howrah, India

Prasun Ghosal, Bengal Engineering & Science University, Howrah, India

Hafizur Rahaman, Bengal Engineering & Science University, Howrah, India

Parthasarathi Dasgupta, Bengal Engineering & Science University, Howrah, India

pp. 73-80

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Design of a MCML Gate Library Applying Multiobjective Optimization (Abstract)

Roberto Pereira-Arroyo, Costa Rica Institute of Technology, Costa Rica

Pablo Alvarado-Moya, Costa Rica Institute of Technology, Costa Rica

Wolfgang H. Krautschneider, Costa Rica Institute of Technology, Costa Rica

pp. 81-85

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A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis (Abstract)

Angelo P. E. Rosiello, DEI - Politecnico di Milano, Italy

Fabrizio Ferrandi, DEI - Politecnico di Milano, Italy

Davide Pandini, STMicroelectronics

Donatella Sciuto, DEI - Politecnico di Milano, Italy

pp. 92-97

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A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing (Abstract)

Hiroki Noguchi, Kobe University

Yusuke Iguchi, Kobe University

Hidehiro Fujiwara, Kobe University

Yasuhiro Morita, Kobe University

Koji Nii, Renesas Technology Corporation, 4-1 Mizuhara, Itami 664-0005, Japan

Hiroshi Kawaguchi, Kobe University, 1-1 Rokkodai, Nada, Kobe, Hyogo 657-8501, Japan

Masahiko Yoshimoto, Kobe University, 1-1 Rokkodai, Nada, Kobe, Hyogo 657-8501, Japan

pp. 107-112

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Design and Analysis of Low Power Dynamic Bus Based on RLC simulation (Abstract)

Shanq-Jang Ruan, National Taiwan University of Science and Technology

Shang-Fang Tsai, National Taiwan University of Science and Technology

Yu-Ting Pai, National Taiwan University of Science and Technology

pp. 113-118

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Overdrive Power-Gating Techniques for Total Power Minimization (Abstract)

Mindaugas Dra?zd?ziulis, Chalmers University of Technology, SE-412 96 G?oteborg, Sweden

Per Larsson-Edefors, Chalmers University of Technology, SE-412 96 G?oteborg, Sweden

Lars "J" Svensson, Chalmers University of Technology, SE-412 96 G?oteborg, Sweden

pp. 125-132

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Coverage Driven Verification applied to Embedded Software (Abstract)

Djones Lettnin, University of Tubingen

Markus Winterholer, Cadence Design Systems

Axel Braun, University of Tubingen

Joachim Gerlach, University of Tubingen

Jurgen Ruf, University of Tubingen

Thomas Kropf, University of Tubingen

Wolfgang Rosenstiel, University of Tubingen

pp. 159-164

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Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation (Abstract)

Tiago R. Balen, Universidade Federal do Rio Grande do Sul, Brazil

Fernanda Lima Kastensmidt, Universidade Federal do Rio Grande do Sul, Brazil

Marcelo S. Lubaszewski, Universidade Federal do Rio Grande do Sul, Brazil

M. Renovell, LIRMM - Montpelier - France

pp. 192-197

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Enhancing the Tolerance to Power-Supply Instability in Digital Circuits (Abstract)

J. Semiao, Univ. of Algarve

J. Freijedo, IST (TUL) / INESC-ID Lisboa

J.J. Rodr?guez Andina, Univ. of Vigo

F. Vargas, PUCRS, Brazil

M. B. Santos, IST (TUL) / INESC-ID Lisboa

I. C. Teixeira, IST (TUL) / INESC-ID Lisboa

J. P. Teixeira, IST (TUL) / INESC-ID Lisboa

pp. 207-212

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An Efficient Analytical Approach to Path-Based Buffer Insertion (Abstract)

Hamid Reza Kheirabadib, Amirkabir University of Technology, Tehran, Iran

Morteza Saheb Zamani, Amirkabir University of Technology, Tehran, Iran

Mehdi Saeedi, Amirkabir University of Technology, Tehran, Iran

pp. 219-224

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Automatic Retargeting of Binary Utilities for Embedded Code Generation (Abstract)

Alexandro Baldassin, State University of Campinas

Paulo Centoducatte, State University of Campinas

Sandro Rigo, State University of Campinas

Daniel Casarotto, Federal University of Santa Catarina

Luiz C. V. Santos, Federal University of Santa Catarina

Max Schultz, Federal University of Santa Catarina

Olinto Furtado, Federal University of Santa Catarina

pp. 253-258

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A Programmable Stream Processing Engine for Packet Manipulation in Network Processors (Abstract)

Michael Meitinger, Munich University of Technology, Arcisstr

Rainer Ohlendorf, Munich University of Technology, Arcisstr

Thomas Wild, Munich University of Technology, Arcisstr

Andreas Herkersdorf, Munich University of Technology, Arcisstr

pp. 259-264

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Design of a Novel CNTFET-based Reconfigurable Logic Gate (Abstract)

J. Liu, Institut des Nanotechnologies de Lyon (INL), France

I. O?Connor, Institut des Nanotechnologies de Lyon (INL), France

D. Navarro, Institut des Nanotechnologies de Lyon (INL), France

F. Gaffiot, Institut des Nanotechnologies de Lyon (INL), France

pp. 285-290

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Inserting Data Encoding Techniques into NoC-Based Systems (Abstract)

Jos? C. S. Palma, PPGC - II - UFRGS - Av.

Leandro Soares null, IndrusiakMES -TU Darmstadt

Fernando G. Moraes, PPGCC - FACIN - PUCRS

Alberto Garcia Ortiz, MES - TU Darmstadt

Manfred Glesner, MES - TU Darmstadt

Ricardo A. L. Reis, PPGC - II - UFRGS - Av.

pp. 299-304

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Application - specific NoC platform design based on System Level Optimization (Abstract)

L. Papadopoulos, Democritus Univ. Thrace, 67100 Xanthi, Greece.

S. Mamagkakis, IMEC, Kapeldreef 75, 3001 Heverlee, Belgium.

F. Catthoor, Katholieke Univ. Leuven, Belgium.

D. Soudris, Democritus Univ. Thrace, 67100 Xanthi, Greece

pp. 311-316

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Fast Complex Valued Matrix Inversion for Multi-User STBC-MIMO Decoding (Abstract)

Di Wu, Linkoping University

Johan Eilert, Linkoping University

Dake Liu, Linkoping University

Dandan Wang, University of Texas at Dallas

Naofal Al-Dhahir, University of Texas at Dallas

Hlaing Minn, University of Texas at Dallas

pp. 325-330

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A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs (Abstract)

Antonino Tumeo, Politecnico di Milano, Italy

Matteo Monchiero, Politecnico di Milano, Italy

Gianluca Palermo, Politecnico di Milano, Italy

Fabrizio Ferrandi, Politecnico di Milano, Italy

Donatella Sciuto, Politecnico di Milano, Italy

pp. 331-336

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Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format (Abstract)

Sreehari Veeramachaneni, International Institute of Information Technology, India

M.Kirthi Krishna, International Institute of Information Technology, India

Lingamneni Avinash, International Institute of Information Technology, India

Reddy P Sreekanth, International Institute of Information Technology, India

M.B. Srinivas, International Institute of Information Technology, India

pp. 343-350

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A Methodology and Toolset to Enable SystemC and VHDL Co-simulation (Abstract)

Richard Maciel, State University of Campinas, Brazil

Bruno Albertini, State University of Campinas, Brazil

Sandro Rigo, State University of Campinas, Brazil

Guido Araujo, State University of Campinas, Brazil

Rodolfo Azevedo, State University of Campinas, Brazil

pp. 351-356

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Investigating Simple Low Latency Reliable Multiported Register Files (Abstract)

Andrew J. Ricketts, Pennsylvania State University

Madhu Mutyam, International Institute of Information Technology, India

N. Vijaykrishnan, Pennsylvania State University

Mary Jane Irwin, Pennsylvania State University

pp. 375-382

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A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs (Abstract)

Prashant Agrawal, CSE, Indian Institute of Technology

Srinivasa R. STG, MG-I, Intel Technology (I)(P) Ltd., India

Ajit N. Oke, MG-I, Intel Technology (I)(P) Ltd., India

Saurabh Vijay, MG-I, Intel Technology (I)(P) Ltd., India

pp. 389-394

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On the Limitations of Power Macromodeling Techniques (Abstract)

Felipe Klein, Institute of Computing, UNICAMP, Brazil

Guido Araujo, Institute of Computing, UNICAMP, Brazil

Rodolfo Azevedo, Institute of Computing, UNICAMP, Brazil

Roberto Leao, UFSC, Brazil

Luiz C. V. Dos Santos, UFSC, Brazil

pp. 395-400

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Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme (Abstract)

K S Sainarayanan, International Institute of Information Technology (IIIT), Hyderabad, India

C Raghunandan, International Institute of Information Technology (IIIT), Hyderabad, India

M B Srinivas, International Institute of Information Technology (IIIT), Hyderabad, India

pp. 401-408

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Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets (Abstract)

Mehrdad Najibi, Amirkabir University of Technology, Iran

Mahtab Niknahad, Amirkabir University of Technology, Iran

Hossein Pedram, Amirkabir University of Technology, Iran

pp. 422-427

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A Novel Reconfigurable Computation Unit for DSP Applications (Abstract)

Jer Min Jou, National Cheng Kung University, Taiwan

Yun-Lung Lee, National Cheng Kung University, Taiwan

Chen-Yen Lin, National Cheng Kung University, Taiwan

Chien-Ming Sun, National Cheng Kung University, Taiwan

pp. 439-444

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Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder (Abstract)

Bruno Zatt, UFRGS - Porto Alegre, RS, Brazil

Arnaldo Azevedo, UFRGS - Porto Alegre, RS, Brazil

Luciano Agostini, UFRGS - Porto Alegre, RS, Brazil

Altamiro Susin, UFRGS - Porto Alegre, RS, Brazil

Sergio Bampi, UFRGS - Porto Alegre, RS, Brazil

pp. 445-446

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Vector Processing Support for FPGA-Oriented High Performance Applications (Abstract)

Hongyan Yang, New Jersey Institute of Technology

Shuai Wang, New Jersey Institute of Technology

Sotirios G. Ziavras, New Jersey Institute of Technology

Jie Hu, New Jersey Institute of Technology

pp. 447-448

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An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb (Abstract)

Antonino Tumeo, Politecnico di Milano, Italy

Matteo Monchiero, Politecnico di Milano, Italy

Gianluca Palermo, Politecnico di Milano, Italy

Fabrizio Ferrandi, Politecnico di Milano, Italy

Donatella Sciuto, Politecnico di Milano, Italy

pp. 449-450

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Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System (Abstract)

S. Corbetta, DEI - Politecnico di Milano

F. Ferrandi, DEI - Politecnico di Milano

M. Morandi, DEI - Politecnico di Milano

M. Novati, DEI - Politecnico di Milano

M.D. Santambrogio, DEI - Politecnico di Milano

D. Sciuto, DEI - Politecnico di Milano

pp. 457-458

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A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator (Abstract)

Luciano Severino de Paula, Federal University of Rio Grande do Sul - UFRGS

Eric Fabris, Federal University of Rio Grande do Sul - UFRGS

Sergio Bampi, Federal University of Rio Grande do Sul - UFRGS

Altamiro Amadeu Susin, Federal University of Rio Grande do Sul - UFRGS

pp. 467-470

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A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation (Abstract)

Mahtab Niknahad, Amirkabir University of Technology, Iran

Behnam Ghavami, Amirkabir University of Technology, Iran

Mehrdad Najibi, Amirkabir University of Technology, Iran

Hossein Pedram, Amirkabir University of Technology, Iran

pp. 471-472

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A comparison of low power architectures for digital delay measurement (Abstract)

Franco Martin-Pirchio, Universidad Nacional del Sur, Bahia Blanca, Argentina

Alfonso Chacon-Rodriguez, Instituto Tecnol?ogico de Costa Rica

Pedro Julian, Universidad Nacional del Sur, Bahia Blanca, Argentina

Pablo Mandolesi, Universidad Nacional del Sur, Bahia Blanca, Argentina

pp. 498-499

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Modeling Subthreshold Leakage Current in General Transistor Networks (Abstract)

Paulo F Butzen, UFRGS, Porto Alegre, Brazil

Andre I. Reis, Nangate Inc., Menlo Park, CA, USA

Chris H. Kim, University of Minnesota, Minneapolis, MN, USA

Renato P. Ribas, UFRGS, Porto Alegre, Brazil

pp. 512-513

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Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures (Abstract)

S. Eachempati, Pennsylvania State University, UP, USA

N. Vijaykrishnan, Pennsylvania State University, UP, USA

Arthur Nieuwoudt, Rice University, Houston, Texas, USA

Yehia Massoud, Rice University, Houston, Texas, USA

pp. 516-517

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