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IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
A comparison of low power architectures for digital delay measurement
Porto Alegre, Brazil
March 09-March 11
ISBN: 0-7695-2896-1
Franco Martin-Pirchio, Universidad Nacional del Sur, Bahia Blanca, Argentina
Alfonso Chacon-Rodriguez, Instituto Tecnol?ogico de Costa Rica
Pedro Julian, Universidad Nacional del Sur, Bahia Blanca, Argentina
Pablo Mandolesi, Universidad Nacional del Sur, Bahia Blanca, Argentina
Two different versions of a method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz are compared in terms of their power dissipation. Power dissipation simulations are run on both versions from their layout on a 0.35?m technology. The second version shows a cut of 37% in total dissipation under the same test conditions.
Citation:
Franco Martin-Pirchio, Alfonso Chacon-Rodriguez, Pedro Julian, Pablo Mandolesi, "A comparison of low power architectures for digital delay measurement," isvlsi, pp.498-499, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007
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