The Binary Signed Digit Number (BSDN) system is used implicitly or explicitly to speed up arithmetic operations in many digital systems. This is due to its capability of carry-free addition and regular layout. Also, with the proper selection of the encoding scheme used to encode the BSDN digit set D={-1, 0, 1} into binary bits, an error detection capability feature can be gained. In this work, we present the design of BSDN full adder cell using the 1-out-of-3 encoding with and without error detection capability. Synthesis results showed that the carry-free addition feature of the BSDN adder is preserved in the proposed design regardless of the inputs size. Also the overall adder performance depends on the desired level of error detection and the effectiveness of the used BSDN full adder.