CSDL - Proceedings I

Symposium Committees (PDF)

pp. xi-xii

Emerging Trends in VLSI

Let?s Think Analog (Abstract)

Melvin A. Breuer, University of Southern California

pp. 2-5

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Analysis of a Mask-Based Nanowire Decoder (Abstract)

Eric Rachlin, Brown University

John E. Savage, Brown University

Benjamin Gojman, Brown University

pp. 6-13

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Bi-Direction Synthesis for Reversible Circuits (Abstract)

Guowu Yang, Portland State University

Xiaoyu Song, Portland State University

William N. N. Hung, Portland State University

Marek A. Perkowski, Portland State University

pp. 14-19

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Advanced VLSI Design

Boost Logic: A High Speed Energy Recovery Circuit Family (Abstract)

Visvesh S. Sathe, University of Michigan

Marios C. Papaefthymiou, University of Michigan

Conrad H. Ziesler, MultiGig Inc.

pp. 22-27

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High Performance Array Processor for Video Decoding (Abstract)

J. Lee, Pennsylvania State University

N. Vijaykrishnan, Pennsylvania State University

M. J. Irwin, Pennsylvania State University

pp. 28-33

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High Speed Redundant Adder and Divider in Output Prediction Logic (Abstract)

Xinyu Guo, University of Washington

Carl Sechen, University of Washington

pp. 34-41

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Sensing Design Issues in Deep Submicron CMOS SRAMs (Abstract)

Aiyappan Natarajan, University of Massachusetts at Amherst

Vijay Shankar, University of Massachusetts at Amherst

Atul Maheshwari, University of Massachusetts at Amherst

Wayne Burleson, University of Massachusetts at Amherst

pp. 42-45

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Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs (Abstract)

Masanori Hariyama, Tohoku University

Weisheng Chong, Tohoku University

Sho Ogata, Tohoku University

Michitaka Kameyama, Tohoku University

pp. 46-50

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VLSI Circuits and Systems

409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS (Abstract)

Sheng Sun, University of Washington

Yi Han, University of Washington

Xinyu Guo, University of Washington

Kian Haur Chong, University of Washington

Larry McMurchie, University of Washington

Carl Sechen, University of Washington

pp. 52-58

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Quasi-Exact BDD Minimization Using Relaxed Best-First Search (Abstract)

Rüdiger Ebendt, University of Bremen

Rolf Drechsler, University of Bremen

pp. 59-64

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Two-Phase Resonant Clock Distribution (Abstract)

Juang-Ying Chueh, University of Michigan

Marios C. Papaefthymiou, University of Michigan

Conrad H. Ziesler, MultiGig Inc.

pp. 65-70

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Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams (Abstract)

Huiying Yang, University of Cincinnati

Anuradha Agarwal, University of Cincinnati

Ranga Vemuri, University of Cincinnati

pp. 71-76

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A Modified Cascaded Sigma-Delta Modulator with Improved Linearity (Abstract)

Ana Rusu, LECS/ICT/Royal Institute of Technology Stockholm and Technical University of Cluj-Napoca

Mohammed Ismail, LECS/ICT/Royal Institute of Technology Stockholm and Ohio State University

Hannu Tenhunen, LECS/ICT/Royal Institute of Technology Stockholm

pp. 77-82

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System-on-a-Chip Design

Jitter in Deep Sub-Micron Interconnect (Abstract)

Jinwook Jang, University of Massachusetts

Sheng Xu, University of Massachusetts

Wayne Burleson, University of Massachusetts

pp. 84-89

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Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCs (Abstract)

Guilin Chen, Pennsylvania State University

Guangyu Chen, Pennsylvania State University

Ozcan Ozturk, Pennsylvania State University

Mahmut Kandemir, Pennsylvania State University

pp. 90-95

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System Level Design

eWatch: Context Sensitive System Design Case Study (Abstract)

Asim Smailagic, Carnegie Mellon University

Daniel P. Siewiorek, Carnegie Mellon University

Uwe Maurer, Carnegie Mellon University

Anthony Rowe, Carnegie Mellon University

Karen P. Tang, Carnegie Mellon University

pp. 98-103

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A Data-Driven Approach for Embedded Security (Abstract)

H. Saputra, Pennsylvania State University

O. Ozturk, Pennsylvania State University

N. Vijaykrishnan, Pennsylvania State University

M. Kandemir, Pennsylvania State University

R. Brooks, Pennsylvania State University

pp. 104-109

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System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures (Abstract)

Vijaykumar Ramamurthi, Arizona State University

Jason McCollum, Arizona State University

Christopher Ostler, Arizona State University

Karam S. Chatha, Arizona State University

pp. 110-116

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Field-Programmable and Reconfigurable Systems

Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures (Abstract)

Alexander Thomas, Universit?t Karlsruhe

J? Becker, Universit?t Karlsruhe

pp. 118-123

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A High Speed Reconfigurable Gate Array for Gigahertz Applications (Abstract)

Jong-Ru Guo, Rensselaer Polytechnic Institute

Chao You, Rensselaer Polytechnic Institute

Michael Chu, Rensselaer Polytechnic Institute

Okan Erdogan, Rensselaer Polytechnic Institute

Russell P. Kraft, Rensselaer Polytechnic Institute

John F. McDonald, Rensselaer Polytechnic Institute

pp. 124-129

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Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2^k (Abstract)

L. Li, Southern Methodist University

Alex Fit-Florea, Southern Methodist University

M. A. Thornton, Southern Methodist University

D. W. Matula, Southern Methodist University

pp. 130-135

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An Improved Dynamic Optically Reconfigurable Gate Array (Abstract)

Minoru Watanabe, Kyushu Institute of Technology

Fuminori Kobayashi, Kyushu Institute of Technology

pp. 136-141

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Lemma Exchange in a Microcontroller Based Parallel SAT Solver (Abstract)

Tobias Schubert, Albert-Ludwigs-University of Freiburg

Bernd Becker, Albert-Ludwigs-University of Freiburg

pp. 142-147

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Application-Specific Low Power VLSI System Design

Power Analysis of Rotary Clock (Abstract)

Zhengtao Yu, North Carolina State University

Xun Liu, North Carolina State University

pp. 150-155

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On Reducing Peak Current and Power during Test (Abstract)

Wei Li, University of Iowa

Sudhakar M. Reddy, University of Iowa

Irith Pomeranz, Purdue University

pp. 156-161

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Design and Implementaion of a 2D-DCT Architecture Using Coefficient Distributed Arithmetic (Abstract)

Soumik Ghosh, University of Louisiana at Lafayette

Soujanya Venigalla, University of Louisiana at Lafayette

Magdy Bayoumi, University of Louisiana at Lafayette

pp. 162-166

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Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths (Abstract)

Ranganath Gopalan, University of South Florida

Chandramouli Gopalakrishnan, University of South Florida

Srinivas Katkoori, University of South Florida

pp. 167-172

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High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization (Abstract)

J. H. Han, University of Edinburgh

A. T. Erdogan, University of Edinburgh and Institute of System Level Integration

T. Arslan, University of Edinburgh and Institute of System Level Integration

pp. 173-178

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Power Awareness in VLSI Design

A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection (Abstract)

V. Mahalingam, University of South Florida

N. Ranganathan, University of South Florida

pp. 180-185

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Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters (Abstract)

Daniel Hostetler, Pennsylvania State University

Yuan Xie, Pennsylvania State University

pp. 186-191

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Test and Verification

Using the Nonlinear Property of FSR and Dictionary Coding for Reduction of Test Volume (Abstract)

Il-Soo Lee, University of Texas at Austin

Jae Hoon Jeong, University of Texas at Austin

Anthony P. Ambler, University of Texas at Austin

pp. 194-199

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Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier (Abstract)

Avijit Dutta, University of Texas at Austin

Terence Rodrigues, University of Texas at Austin

Nur A. Touba, University of Texas at Austin

pp. 200-205

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Fault Diagnosis and Fault Model Aliasing (Abstract)

Irith Pomeranz, Purdue University

Srikanth Venkataraman, Intel Corporation

Sudhakar M. Reddy, University of Iowa

pp. 206-211

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PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits (Abstract)

Junhao Shi, University of Bremen and Philips Semiconductors GmbH

G?rschwin Fey, University of Bremen and Philips Semiconductors GmbH

Rolf Drechsler, University of Bremen and Philips Semiconductors GmbH

Andreas Glowatz, University of Bremen and Philips Semiconductors GmbH

Friedrich Hapke, University of Bremen and Philips Semiconductors GmbH

J? Schl?ffel, University of Bremen and Philips Semiconductors GmbH

pp. 212-217

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Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators (Abstract)

Tian Xia, University of Vermont

Hao Zheng, University of South Florida

Jing Li, IBM Microelectronics Division

Ahmed Ginawi, IBM Microelectronics Division

pp. 218-223

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Physical Design

IR Drop and Ground Bounce Awareness Timing Model (Abstract)

Muzhou Shao, Synopsys Inc.

Youxin Gao, Synopsys Inc.

Li-Pen Yuan, Synopsys Inc.

Martin D. F. Wong, University of Illinois at Urbana-Champaign

pp. 226-231

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Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources (Abstract)

Deepak Rautela, North Dakota State University

Rajendra Katti, North Dakota State University

pp. 232-237

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Post-Placement Pin Optimiztion (Abstract)

Jurjen Westra, Eindhoven University of Technology

Patrick Groeneveld, Eindhoven University of Technology

pp. 238-243

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Poster Papers

A Low Power Embedded Dataflow Coprocessor (PDF)

Yijun Liu, University of Manchester

Steve Furber, University of Manchester

pp. 246-247

Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits (PDF)

Saraju P. Mohanty, University of North Texas

R. Velagapudi, University of North Texas

V. Mukherjee, University of North Texas

Hao Li, University of South Florida

pp. 248-249

Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs (PDF)

Renqiu Huang, University of Cincinnati

Ranga Vemuri, University of Cincinnati

pp. 250-251

Analysis of Incremental Communication for Multilayer Neural Networks on a Field Programmable Gate Array (Abstract)

Joshua R. Dick, University of New Brunswick

Kenneth B. Kent, University of New Brunswick

pp. 252-254

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Reduction of Power and Test Time by Removing Cluster of Don?t-Care from Test Data Set (PDF)

Il-Soo Lee, University of Texas at Austin

Yu-Ting Lin, University of Texas at Austin

Anthony P. Ambler, University of Texas at Austin

pp. 255-256

Evaluating the Data Integrity of Memory Systems by Configurable Markov Models (Abstract)

M. Ottavi, Northeastern University Boston

L. Schiano, Northeastern University Boston

F. Lombardi, Northeastern University Boston

S. Pontarelli, University of Rome

G. C. Cardarilli, University of Rome

pp. 257-259

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Synthesis of Self-Resetting Stage Logic Pipelines (Abstract)

Abdelhalim Alsharqawi, University of Central Florida

Abdel Ejnioui, University of Central Florida

pp. 260-262

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Energy Efficient Architectures for the Log-MAP Decoder through Intelligent Memory Usage (Abstract)

Indrajit Atluri, University of Edinburgh

Ashwin K. Kumaraswamy, University of Loughborough

pp. 263-265

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RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis (PDF)

Kaiping Zeng, Darmstadt University of Technology

Sorin A. Huss, Darmstadt University of Technology

pp. 266-267

Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses (PDF)

Bertrand Le Gal, University of South Brittany

Emmanuel Casseau, University of South Brittany

Sylvain Huet, University of South Brittany

Eric Martin, University of South Brittany

pp. 268-269

The Use of Pre-Evaluation Phase in Dynamic CMOS Logic (PDF)

A. Rao, Southern Illinois University

Th. Haniotakis, Southern Illinois University

Y. Tsiatouhas, University of Ioannina

H. Djemil, Southern Illinois University

pp. 270-271

Configurable Multiprocessors for High-Performance MPEG-4 Video Coding (PDF)

V. A. Chouliaras, Loughborough University

T. R. Jacobs, Loughborough University

Ashwin K. Kumaraswamy, Loughborough University

Jose L. Nunez-Yanez, University of Bristol

pp. 272-273

Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs (PDF)

Mototsugu Miyano, Kyushu Institute of Technology

Minoru Watanabe, Kyushu Institute of Technology

Fuminori Kobayashi, Kyushu Institute of Technology

pp. 274-275

Wire Length Distribution Model Considering Core Utilization for System on Chip (PDF)

Takanori Kyogoku, Tokyo Institute of Technology

Junpei Inoue, Tokyo Institute of Technology

Hidenari Nakashima, Tokyo Institute of Technology

Takumi Uezono, Tokyo Institute of Technology

Kenichi Okada, Tokyo Institute of Technology

Kazuya Masu, Tokyo Institute of Technology

pp. 276-277

12-23 GHz Ultra Wide Tuning Range Voltage-Controlled Ring Oscillator with Hybrid Control Schemes (PDF)

Young Uk Yim, Rensselaer Polytechnic Institute

John F McDonald, Rensselaer Polytechnic Institute

Russell P. Kraft, Rensselaer Polytechnic Institute

pp. 278-279

A Flexible and Efficient Hardware Architecture for Real-Time Face Recognition Based on Eigenface (PDF)

Hau T. Ngo, Old Dominion University

Rajkiran Gottumukkal, Old Dominion University

Vijayan K. Asari, Old Dominion University

pp. 280-281

A High Performance Hybrid Wave-Pipelined Multiplier (PDF)

Suryanarayana B. Tatapudi, Washington State University

Jos? G. Delgado-Frias, Washington State University

pp. 282-283

Towards Integration of Quadratic Placement and Pin Assignment (Abstract)

Jurjen Westra, Eindhoven University of Technology

Patrick Groeneveld, Eindhoven University of Technology

pp. 284-286

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Balancing System Level Pipelines with Stage Voltage Scaling (Abstract)

Hui Guo, University of New South Wales

Sri Parameswaran, University of New South Wales

pp. 287-289

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Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator (PDF)

A. Maili, Graz University of Technology

C. Steger, Graz University of Technology

R. Wei?, Graz University of Technology

R. Quigley, University College Dublin

D. Dalton, University College Dublin

pp. 290-291

Design of a QCA Memory with Parallel Read/Serial Write (Abstract)

M. Ottavi, Northeastern University Boston

V. Vankamamidi, Northeastern University Boston

F. Lombardi, Northeastern University Boston

S. Pontarelli, University of Rome

A. Salsano, University of Rome

pp. 292-294

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RG-SRAM: A Low Gate Leakage Memory Design (PDF)

Charan Thondapu, State University of New York at Buffalo

Praveen Elakkumanan, State University of New York at Buffalo

Ramalingam Sridhar, State University of New York at Buffalo

pp. 295-296

Increasing Data TLB Resilience to Transient Errors (PDF)

Feihui Li, Pennsylvania State University

Mahmut Kandemir, Pennsylvania State University

pp. 297-298

RITC: Repeater Insertion with Timing Target Compensation (PDF)

Yuantao Peng, North Carolina State University

Xun Liu, North Carolina State University

pp. 299-300

Design of a Real Time System for Nonlinear Enhancement of Video Streams by an Integrated Neighborhood Dependent Approach (PDF)

Adam Livingston, Old Dominion University

Hau Ngo, Old Dominion University

Ming Zhang, Old Dominion University

Li Tao, Old Dominion University

Vijayan K. Asari, Old Dominion University

pp. 301-302

An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels (PDF)

Ming Z. Zhang, Old Dominion University

Hau T. Ngo, Old Dominion University

Adam R. Livingston, Old Dominion University

Vijayan K. Asari, Old Dominion University

pp. 303-304

A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation (PDF)

Oswaldo Cadenas, University of Reading

Graham Megson, University of Reading

Daniel Jones, University of Reading

pp. 305-306

A Hierachical Method for Wiring and Congestion Prediction (PDF)

Fei He, Tsinghua University

Xiaoyu Song, Portland State University

Lerong Cheng, University of California at Los Angeles

Guowu Yang, Portland State University

Zhiwei Tang, Portland State University

Ming Gu, Tsinghua University

Jiaguang Sun, Tsinghua University

pp. 307-308

CMOS Realization of Online Testable Reversible Logic Gates (PDF)

D. P. Vasudevan, University of Arkansas

P. K. Lala, University of Arkansas

J. P. Parkerson, University of Arkansas

pp. 309-310

A Scalable Parallel SoC Architecture for Network Processors (Abstract)

J?rg-Christian Niemann, University of Paderborn

Mario Porrmann, University of Paderborn

Ulrich R?ckert, University of Paderborn

pp. 311-313

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A Comparative Study on Dicing of Multiple Project Wafers (PDF)

Meng-Chiou Wu, Yuan Ze University

Rung-Bin Lin, Yuan Ze University

pp. 314-315

Author Index

Author Index (PDF)

pp. 317-319