Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2^k

L. Li; D. W. Matula; Alex Fit-Florea; M. A. Thornton

doi:10.1109/ISVLSI.2005.35

I
ISVLSI
2005
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)
Abstract - Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2^k

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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2^k

Tampa, Florida

May 11-May 12

ISBN: 0-7695-2365-X

	ASCII Text	x
	L. Li, Alex Fit-Florea, M. A. Thornton, D. W. Matula, "Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2^k," VLSI, IEEE Computer Society Annual Symposium on, pp. 130-135, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005.

	BibTex	x
	@article{ 10.1109/ISVLSI.2005.35, author = {L. Li and Alex Fit-Florea and M. A. Thornton and D. W. Matula}, title = {Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2^k}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2365-X}, pages = {130-135}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.35}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2^k SN - 0-7695-2365-X SP130 EP135 A1 - L. Li, A1 - Alex Fit-Florea, A1 - M. A. Thornton, A1 - D. W. Matula, PY - 2005 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

L. Li, Southern Methodist University

Alex Fit-Florea, Southern Methodist University

M. A. Thornton, Southern Methodist University

D. W. Matula, Southern Methodist University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.35

We describe the hardware implementation of a novel algorithm for computing the discrete logarithm modulo 2^k. The circuit has a total latency of less than k table-lookup-determined shift-and-add modulo 2^k operations. We introduce a one-to-one mapping between k-bit binary integers and k-bit encodings of a factorization of the integers employing the discrete logarithm. We compare the physical layout result for the circuit when k=8, 16, 32, and 64.

Citation:

L. Li, Alex Fit-Florea, M. A. Thornton, D. W. Matula, "Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2^k," isvlsi, pp.130-135, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005

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