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IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04)
Lafayette, Louisiana
February 19-February 20
ISBN: 0-7695-2097-9
| ASCII Text | x | ||
| Sangjin Hong, Shu-Shin Chin, "Incorporating Power Reduction Mechanism in Arithmetic Core Design," VLSI, IEEE Computer Society Annual Symposium on, pp. 249, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004. | |||
| BibTex | x | ||
| @article{ 10.1109/ISVLSI.2004.1339544, author = {Sangjin Hong and Shu-Shin Chin}, title = {Incorporating Power Reduction Mechanism in Arithmetic Core Design}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2004}, isbn = {0-7695-2097-9}, pages = {249}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339544}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Incorporating Power Reduction Mechanism in Arithmetic Core Design SN - 0-7695-2097-9 SP EP A1 - Sangjin Hong, A1 - Shu-Shin Chin, PY - 2004 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER - | |||
A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. The mechanism eliminates power dissipated by the glitching while it maintains the speed. The mechanismcan be applied to either fully combinational or pipelined array structures such as parallel multipliers and/or CORDICs. The mechanism is easily incorporated such that no circuit change in the existing array structure is necessary.
Citation:
Sangjin Hong, Shu-Shin Chin, "Incorporating Power Reduction Mechanism in Arithmetic Core Design," isvlsi, pp.249, IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (ISVLSI'04), 2004
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