CSDL - Proceedings I

Message from the Technical Program Chairs (PDF)

pp. xi

Symposium Committees (PDF)

pp. xii

Panels (PDF)

pp. xiv

Emerging Trends in VLSI Systems

Toward Design Technology in 2020: Trends, Issues, and Challenges (PDF)

Justin E. Harlow III, Semiconductor Research Corporation

pp. 3

Future Challenges in VLSI Design (Abstract)

José A. B. Fortes, University of Florida

pp. 5

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Networks-On-Chip:The Quest for On-Chip Fault-Tolerant Communication (Abstract)

Radu Marculescu, Carnegie Mellon University

pp. 8

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Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools (Abstract)

Shamik Das, Massachusetts Institute of Technology

Anantha Chandrakasan, Massachusetts Institute of Technology

Rafael Reif, Massachusetts Institute of Technology

pp. 13

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Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory (Abstract)

Sarah E. Frost, University of Notre Dame

Arun F. Rodrigues, University of Notre Dame

Charles A. Giefer, University of Notre Dame

Peter M. Kogge, University of Notre Dame

pp. 19

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Advanced VLSI Design

Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS (Abstract)

Koushik K. Das, University of Michigan

Richard B. Brown, University of Michigan

pp. 29

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Power Comparison of Throughput Optimized IC Busses (Abstract)

E. Malley, Carnegie Mellon University

A. Salinas, Carnegie Mellon University

K. Ismail, Carnegie Mellon University

L. Pileggi, Carnegie Mellon University

pp. 35

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LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits (Abstract)

Yonghee Im, Purdue University

Kaushik Roy, Purdue University

pp. 45

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VLSI Circuits and Systems

Interconnect Effort - A Unification of Repeater Insertion and Logical Effort (Abstract)

Srividya Srinivasaraghavan, University of Massachusetts

Wayne Burleson, University of Massachusetts

pp. 55

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Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design (Abstract)

Makram M. Mansour, University of Illinois at Urbana-Champaign

Mohammad M. Mansour, University of Illinois at Urbana-Champaign

Amit Mehrotra, University of Illinois at Urbana-Champaign

pp. 62

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A Fine-Grain Phased Logic CPU (Abstract)

Robert B. Reese, Mississippi State University

Mitchell A. Thornton, Southern Methodist University

Cherrice Traver, Union College

pp. 70

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An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters (Abstract)

Kwang-Hyun Baek, Rockwell Scientific Company

Myung-Jun Choe, Rockwell Scientific Company

Sung-Mo (Steve) Kang, University of California

pp. 80

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System-on-a-Chip Design

Energy Benefits of a Configurable Line Size Cache for Embedded Systems (Abstract)

Chuanjun Zhang, University of California, Riverside

Frank Vahid, University of California, Riverside

Walid Najjar, University of California, Riverside

pp. 87

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Reconfigurable Fast Memory Management System Design for Application Specific Processors (Abstract)

S. Kagan Agun, Illinois Institute of Technology

Morris Chang, Illinois Institute of Technology

pp. 92

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System Level Design

System Design Approach To Power Aware Mobile Computers (Abstract)

J. Warren, Carnegie Mellon University

T. Martin, Carnegie Mellon University

A. Smailagic, Carnegie Mellon University

D. P. Siewiorek, Carnegie Mellon University

pp. 101

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Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC) (Abstract)

Jürgen Becker, Universitaet Karlsruhe (TH)

Martin Vorbach, PACT XPP Technologies AG

pp. 107

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A Framework for Security on NoC Technologies (Abstract)

Catherine H. Gebotys, University of Waterloo

Robert J. Gebotys, Wilfrid Laurier University

pp. 113

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Low Power VLSI System Design I

Peak Power Minimization Through Datapath Scheduling (Abstract)

Saraju P. Mohanty, University of South Florida

N. Ranganathan, University of South Florida

Sunil K. Chappidi, University of South Florida

pp. 121

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Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch (Abstract)

J. S. Hu, The Pennsylvania State University

N. Vijaykrishnan, The Pennsylvania State University

M. J. Irwin, The Pennsylvania State University

M. Kandemir, The Pennsylvania State University

pp. 127

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Energy Recovering ASIC Design (Abstract)

Conrad H. Ziesler, University of Michigan

Joohee Kim, University of Michigan

Marios C. Papaefthymiou, University of Michigan

pp. 133

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A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors (Abstract)

Yu Bai, Brown University

R. Iris Bahar, Brown University

pp. 139

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Low Power VLSI System Design II

An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages (Abstract)

Robert Bai, University of Michigan

Sarvesh Kulkarni, University of Michigan

Wesley Kwong, University of Michigan

Ashish Srivastava, University of Michigan

Dennis Sylvester, University of Michigan

David Blaauw, University of Michigan

pp. 149

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Low Power Test Set Embedding Based on Phase Shifters (Abstract)

Maciej Bellos, University of Patras; Computer Technology Institute

Dimitri Kagaris, Southern Illinois University

Dimitris Nikolos, University of Patras; Computer Technology Institute

pp. 155

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Supply Voltage Scalable System Design Using Self-Timed Circuits (Abstract)

W. Kuang, University of Central Florida

J.S. Yuan, University of Central Florida

A. Ejnioui, University of Central Florida

pp. 161

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Optimal shielding/spacing metrics for low power design (Abstract)

Ravishankar Arunachalam, I.B.M Electronic Design Automation

Emrah Acar, I.B.M Austin Research Lab

Sani R. Nassif, I.B.M Austin Research Lab

pp. 167

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An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs (Abstract)

Abdulkadir Utku Diril, Georgia Institute of Technology

Yuvraj Singh Dhillon, Georgia Institute of Technology

Kyu-won Choi, Georgia Institute of Technology

Abhijit Chatterjee, Georgia Institute of Technology

pp. 173

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Physical Design, Synthesis and Optimization

Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization (Abstract)

Andrew B. Kahng, UC San Diego

Bao Liu, UC San Diego

pp. 183

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Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies (Abstract)

Mohamed A. Elgamel, University of Louisiana at Lafayette

Kannan S. Tharmalingam, University of Louisiana at Lafayette

Magdy A. Bayoumi, University of Louisiana at Lafayette

pp. 189

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Block-wise Extraction of Rent?s Exponents for an Extensible Processor (Abstract)

Tapani Ahonen, Tampere University of Technology

Tero Nurmi, University of Turku

Jari Nurmi, Tampere University of Technology

Jouni Isoaho, University of Turku

pp. 193

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Poster Papers

A Novel Technique for Noise-Tolerance in Dynamic Circuits (Abstract)

Sumeer Goel, University of Louisiana at Lafayette

Tarek Darwish, University of Louisiana at Lafayette

Magdy Bayoumi, University of Louisiana at Lafayette

pp. 203

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EFFICIENT VLSI IMPLEMENTATION OF A VLC DECODER FOR UNIVERSAL VARIABLE LENGTH CODE (PDF)

Shang Xue, Mid Sweden University

Bengt Oelmann, Mid Sweden University

pp. 207

AN AREA-EFFICIENT EUCLIDEAN ALGORITHM BLOCK FOR REED-SOLOMON DECODER (PDF)

Hanho Lee, University of Connecticut

pp. 209

An Architectural Leakage Power Simulator for VHDL Structural Datapaths (PDF)

Chandramouli Gopalakrishnan, University of South Florida

Srinivas Katkoori, University of South Florida

pp. 211

Systolic Array Implementation of Block Based Hopfield Neural Network for Pattern Association (PDF)

Ming-Jung Seow, Old Dominion University

Hau Ngo, Old Dominion University

Vijayan Asari, Old Dominion University

pp. 213

Pre-computatio of Rotatio Bits in Unidirectional CORDIC for Trigonometric and Hyperbolic Computations (PDF)

Satish Ravichandran, Old Dominion University

Vijayan Asari, Old Dominion University

pp. 215

Self-Timed Design with Dynamic Domino Circuits (Abstract)

Jung-Lin Yang, University of Utah

Erik Brunvand, University of Utah

pp. 217

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Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses (PDF)

JIANGJIANG LIU, University at Buffalo

NIHAR R. MAHAPATRA, University at Buffalo

KRISHNAN SUNDARESAN, University at Buffalo

pp. 220

Automated Dynamic Memory Data Type Implementation Exploration and Optimization (Abstract)

Marc Leeman, ESAT K.U. Leuven

Chantal Ykman, ESAT K.U. Leuven

David Atienza, ESAT K.U. Leuven

Vincenzo De Florio, ESAT K.U. Leuven

Geert Deconinck, ESAT K.U. Leuven

pp. 222

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Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects (Abstract)

Per Larsson-Edefors, Chalmers University of Technology

Daniel Eckerbert, Chalmers University of Technology

Henrik Eriksson, Chalmers University of Technology

Lars "J" Svensson, Chalmers University of Technology

pp. 225

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Decoder-Based Multi-Context Interconnect Architecture (Abstract)

Andrea Lodi, University of Bologna

Luca Ciccarelli, University of Bologna

Andrea Cappelli, University of Bologna

Fabio Campi, University of Bologna

Mario Toma, University of Bologna

pp. 231

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Titan II : An IPComp Processor for 10Gbit/sec networks (PDF)

Ioannis Papaefstathiou, Institute of Computer Science

pp. 234

Frequency Domain Approach for CMOS Ultra-Wideband Radios (PDF)

Hyung-Jin Lee, VTVT (Virginia Tech VLSI for Telecommunications) Lab

Dong Sam Ha, VTVT (Virginia Tech VLSI for Telecommunications) Lab

pp. 236

Getting High-Performance Silicon from System-Level Design (Abstract)

W. Rhett Davis, North Carolina State University

pp. 238

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Testable Sequential Circuit Design:Partitioning for Pseudoexhaustive Test (PDF)

Bassam Shaer, Department of Electrical & Computer Engineering, UMD

Kailash Aurangabadkar, Department of Computer Science, UMD

Nitin Agarwal, Department of Computer Science, UMD

pp. 244

Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering (Abstract)

Shalini Ghosh, University of Texas, Austin

Sugato Basu, University of Texas, Austin

Nur A. Touba, University of Texas, Austin

pp. 246

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Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization (PDF)

Luca Benini, Universit? di Bologna

Davide Bruni, Universit? di Bologna

Alberto Macii, Politecnico di Torino

Enrico Macii, Politecnico di Torino

pp. 250

Dynamic Coding Technique For Low-Power Data Bus (PDF)

M. Madhu, Indian Institute of Technology Madras

V. Srinivasa Murty, Indian Institute of Technology Madras

V. Kamakoti, Indian Institute of Technology Madras

pp. 252

Dynamic Coding Technique For Low-Power Data Bus (Abstract)

Hongping Li, University of Oklahoma

John K. Antonio, University of Oklahoma

Sudarshan K. Dhall, University of Oklahoma

pp. 254

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HIGH THROUGHPUT POWER-AWARE FIR FILTER DESIGN BASED ON FINE-GRAIN PIPELINING MULTIPLIERS AND ADDERS (PDF)

Jia Di, University of Central Florida

J. S. Yuan, University of Central Florida

R. Demara, University of Central Florida

pp. 260

Code Compression Techniques for Embedded Systems and Their Effectiveness (PDF)

KRISHNAN SUNDARESAN, University at Buffalo

NIHAR R. MAHAPATRA, University at Buffalo

pp. 262

Random Characterization of Design Automation Algorithms (PDF)

Sandeep K. Kondapuram, University of South Florida

Peter M. Maurer, Baylor University

pp. 264

Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing (Abstract)

Hua Tang, State University of New York at Stony Brook

Hui Zhang, State University of New York at Stony Brook

Alex Doboli, State University of New York at Stony Brook

pp. 266

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Equalizing Filter Design for Crosstalk Cancellation (Abstract)

Jihong Ren, University of British Columbia

Mark Greenstreet, University of British Columbia

pp. 272

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Behavioral Simulation of Power Line Noise Coupling in Mixed-Signal Systems using SystemC (Abstract)

Jan Lundgren, Mid Sweden University

Bengt Oelmann, Mid Sweden University

Trond Ytterdal, Norwegian Univ.of Science and Technology

Patrik Eriksson, Acreo AB, System Level Integration

Munir Abdalla, Mid Sweden University

Mattias O'Nils, Mid Sweden University

pp. 275

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Enhanced Techniques for Current Balanced Logic in Mixed-Signal ICs (PDF)

Li Yang, University of Central Florida

J. S. Yuan, University of Central Florida

pp. 278

Quantum Voltage Comparator for 0.07 ?m CMOS Flash A/D Converters (PDF)

Jincheol Yoo, The Pennsylvania State University

Kyusun Choi, The Pennsylvania State University

Jahan Ghaznavi, The Pennsylvania State University

pp. 280

Author's Index (PDF)

pp. 283