CSDL - Proceedings I

Message from the Technical Program Chairs (PDF)

pp. x

Symposium Committees (PDF)

pp. xi

Panels (PDF)

pp. xiii

Emerging Trends in VLSI Systems

VLSI Systems for Embedded Video (Abstract)

Wayne Wolf, Princeton University

Burak Ozer, Princeton University

Tiehan Lv, Princeton University

pp. 0003

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Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits (Abstract)

Alice Wang, Massachusetts Institute of Technology

Anantha P. Chandrakasan, Massachusetts Institute of Technology

Stephen V. Kosonocky, IBM T.J. Watson Research Center

pp. 0007

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System Level Design

System Design and Power Optimization for Mobile Computers (Abstract)

Asim Smailagic, Carnegie Mellon University

Matthew Ettus, Carnegie Mellon University

pp. 0015

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Hardware-Software Co-Adaptation for Data-Intensive Embedded Applications (Abstract)

I. Kadayif, Pennsylvania State University

M. Kandemir, Pennsylvania State University

N. Vijaykrishnan, Pennsylvania State University

M. J. Irwin, Pennsylvania State University

pp. 0020

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A Low Power High Performance Distributed DCT Architecture (Abstract)

Ahmed Shams, Intel Inc.

Wendi Pan, University of Louisiana

Archana Chidanandan, University of Louisiana

Magdy Bayoumi, University of Louisiana

pp. 0026

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Advanced VLSI Design

Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach (Abstract)

Vikas Chandra, Carnegie Mellon University

Herman Schmit, Carnegie Mellon University

pp. 0035

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Optimal Timing for Skew-Tolerant High-Speed Domino Logic (Abstract)

Seong-Ook Jung, University of Illinois at Urbana-Champaign

Ki-Wook Kim, Pluris Inc.

Steve Kang, University of California at Santa Cruz

pp. 0041

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Multi-Output Timed Shannon Circuits (Abstract)

Mitchell A. Thornton, Mississippi State University

Rolf Drechsler, University of Bremen

D. Michael Miller, University of Victoria

pp. 0047

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Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation (Abstract)

Adnan Abdul-Aziz Gutub, Oregon State University

Alexandre Ferreira Tenca, Oregon State University

Cetin Kaya Koç, Oregon State University

pp. 0053

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Low Power VLSI System Design

Impact of Technology Scaling in the Clock System Power (Abstract)

David Duarte, Pennsylvania State University

Narayanan Vijaykrishnan, Pennsylvania State University

Mary Jane Irwin, Pennsylvania State University

pp. 0059

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Datapath Scheduling using Dynamic Frequency Clocking (Abstract)

Saraju P. Mohanty, University of South Florida

N. Ranganathan, University of South Florida

V. Krishna, Agilent Technology

pp. 0065

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Temperature Variable Supply Voltage for Power Reduction (Abstract)

Kaveh Shakeri, Georgia Institute of Technology

James D. Meindl, Georgia Institute of Technology

pp. 0071

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Force-Directed Scheduling for Dynamic Power Optimization (Abstract)

Suvodeep Gupta, University of South Florida

Srinivas Katkoori, University of South Florida

pp. 0075

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VLSI Circuits and Systems

Efficient Adder Circuits Based on a Conservative Reversible Logic Gate (Abstract)

J.W. Bruce, Mississippi State University

M.A. Thornton, Mississippi State University

L. Shivakumaraiah, Mississippi State University

P.S. Kokate, Mississippi State University

X. Li, Mississippi State University

pp. 0083

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Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops (Abstract)

Mohamed Elgamel, University of Louisiana at Lafayette

Tarek Darwish, University of Louisiana at Lafayette

Magdy Bayoumi, University of Louisiana at Lafayette

pp. 0089

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High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph (Abstract)

Naotaka Ohsawa, Tohoku University

Masanori Hariyama, Tohoku University

Michitaka Kameyama, Tohoku University

pp. 0095

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VLSI Implementation for MAC-Level DWT Architecture (Abstract)

Shiuh-Rong Huang, National Chiao-Tung University

Lan-Rong Dung, National Chiao-Tung University

pp. 0101

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Speedup of Self-Timed Digital Systems Using Early Completion (Abstract)

Scott C. Smith, University of Missouri at Rolla

pp. 0107

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System-on-a-Chip Design

A Network on Chip Architecture and Design Methodology (Abstract)

Shashi Kumar, Royal Institute of Technology

Axel Jantsch, Royal Institute of Technology

Mikael Millberg, Royal Institute of Technology

Johny Öberg, Royal Institute of Technology

Juha-Pekka Soininen, VTT Electronics

Martti Forsell, VTT Electronics

Kari Tiensyrjä, VTT Electronics

Ahmed Hemani, Spirea AB

pp. 0117

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A High Speed Shift-Invariant Wavelet Transform Chip for Video Compression (Abstract)

Henry Y.H. Chuang, University of Pittsburgh

David P. Birch, University of Pittsburgh

Li-Chang Liu, University of Pittsburgh

Jong-Chih Chien, University of Pittsburgh

Steve P. Levitan, University of Pittsburgh

C. C. Li, University of Pittsburgh

pp. 0125

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Physical Design, Synthesis, and Optimization

Accelerating Retiming Under the Coupled-Edge Timing Model (Abstract)

Ingmar Neumann, University of Kaiserslautern

Kolja Sulimma, University of Kaiserslautern

Wolfgang Kunz, University of Kaiserslautern

pp. 0135

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Automated Synthesis of Standard Cells using Genetic Algorithms (Abstract)

Anil Bahuman, University of Georgia

Benjamin Bishop, University of Georgia

Khaled Rasheed, University of Georgia

pp. 0141

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Test and Verification

Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation (Abstract)

Markus Wedler, University of Kaiserslautern

Dominik Stoffel, University of Kaiserslautern

Wolfgang Kunz, University of Kaiserslautern

pp. 0151

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An Efficient Partitioning Algorithm of Combinational CMOS Circuits (Abstract)

Bassam Shaer, Universityof Minnesota at Duluth

Khaled Dib, Universityof Minnesota at Duluth

pp. 0159

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A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test (Abstract)

Srdjan Dragic, University of Alberta

Martin Margala, University of Rochester

pp. 0165

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Author Index (PDF)

pp. 0171