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IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02)
Efficient Adder Circuits Based on a Conservative Reversible Logic Gate
Pittsburgh, Pennsylvania
April 25-April 26
ISBN: 0-7695-1486-3
| ASCII Text | x | ||
| J.W. Bruce, M.A. Thornton, L. Shivakumaraiah, P.S. Kokate, X. Li, "Efficient Adder Circuits Based on a Conservative Reversible Logic Gate," VLSI, IEEE Computer Society Annual Symposium on, pp. 0083, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02), 2002. | |||
| BibTex | x | ||
| @article{ 10.1109/ISVLSI.2002.1016879, author = {J.W. Bruce and M.A. Thornton and L. Shivakumaraiah and P.S. Kokate and X. Li}, title = {Efficient Adder Circuits Based on a Conservative Reversible Logic Gate}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2002}, isbn = {0-7695-1486-3}, pages = {0083}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2002.1016879}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Efficient Adder Circuits Based on a Conservative Reversible Logic Gate SN - 0-7695-1486-3 SP EP A1 - J.W. Bruce, A1 - M.A. Thornton, A1 - L. Shivakumaraiah, A1 - P.S. Kokate, A1 - X. Li, PY - 2002 VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER - | |||
Conservative and reversible logic gates are widely known to be compatible with revolutionary computing paradigms such as optical and quantum computing. A fundamental conservative reversible logic gate is the Fredkin gate. This paper presents efficient adder circuits based on the Fredkin gate. Novel full adder circuits using Fredkin gates are proposed which have lower hardware complexity than the current state-of-the-art, while generating the additional signals required for carry skip adder architectures. The traditional ripple carry adder and several carry skip adder topologies are compared. Theoretical performance of each adder is determined and compared. Although the variable sized block carry skip adder is determined to have shorter delay than the fixed block size carry skip adder, the performance gains are not sufficient to warrant the required additional hardware complexity.
Citation:
J.W. Bruce, M.A. Thornton, L. Shivakumaraiah, P.S. Kokate, X. Li, "Efficient Adder Circuits Based on a Conservative Reversible Logic Gate," isvlsi, pp.0083, IEEE Computer Society Annual Symposium on VLSI (ISVLSI'02), 2002
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