In this paper, we describe a new datapath scheduling algorithm called DFCS based on the concept of dynamic frequency clocking. In dynamic frequency clocking scheme, all functional units in the datapath are driven by a single clock line that switches frequency dynamically at run time. The algorithm schedules lower frequency operators at earlier steps and delays higher frequency operators to later steps. Next, it regroups some of the higher frequency operators with low frequency operators so as to meet the time constraint. During this phase, DFCS assignes the frequency for each cycle and the functional unit with the corresponding voltage. The algorithm has been applied to various high level synthesis benchmark circuits under different time constraints. The experimental results show that using three supply voltage levels (5.0V, 3.3V, 2.4V) and time constraints ({1.5, 1.75 and 2.0} * the critical path delay), average energy savings in the range of 46% to 68% is obtained with respect to using a single-frequency and single-voltage scheme.