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Proceedings of the 15th international symposium on System Synthesis (ISSS '02)
System-Level Modeling of a Network Switch SoC
Kyoto, Japan
October 02-October 04
ISBN: 1-58113-576-9
| ASCII Text | x | ||
| Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul, "System-Level Modeling of a Network Switch SoC," System Synthesis, International Symposium on, pp. 62-67, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002. | |||
| BibTex | x | ||
| @article{ 10.1109/ISSS.2002.1227153, author = {Andrew S. Cassidy and Christopher P. Andrews and Donald E. Thomas and JoAnn M. Paul}, title = {System-Level Modeling of a Network Switch SoC}, journal ={System Synthesis, International Symposium on}, volume = {0}, year = {2002}, isbn = {1-58113-576-9}, pages = {62-67}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227153}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - System Synthesis, International Symposium on TI - System-Level Modeling of a Network Switch SoC SN - 1-58113-576-9 SP62 EP67 A1 - Andrew S. Cassidy, A1 - Christopher P. Andrews, A1 - Donald E. Thomas, A1 - JoAnn M. Paul, PY - 2002 KW - computer-aided design KW - memory visualization level design KW - network switch KW - performance modeling KW - system modeling VL - 0 JA - System Synthesis, International Symposium on ER - | |||
We present the modeling of the high-level design of a next generation network switch from the perspective of a Computer-Aided Design (CAD) team within the larger context of a design team consisting of an experienced network switch designer and an experienced VLSI hardware designer. After facilitating the design process, the CAD team observed how designers approach high-level designs, beyond RTL. We motivate the need for CAD support that allows designers to effectively manipulate what we refer to as Memory Visualization Level (MVL) design.
Index Terms:
computer-aided design, memory visualization level design, network switch, performance modeling, system modeling
Citation:
Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul, "System-Level Modeling of a Network Switch SoC," isss, pp.62-67, Proceedings of the 15th international symposium on System Synthesis (ISSS '02), 2002
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