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13th International Symposium on System Synthesis (ISSS'00)
Madrid, Spain
September 20-September 22
ISBN: 0-7695-0765-4
Table of Contents
Session 1: System Level Design Research in an Industrial Setting (Invited Talks): Organizer and Chair: Don MacMillen
Vivek Sinha, University of California at Irvine
Frederic Doucet, University of California at Irvine
Chuck Siska, University of California at Irvine
Rajesh Gupta, University of California at Irvine
Stan Liao, Synopsys Inc.
Abhijit Ghosh, Synopsys Inc.
pp. 9
The Nimble Compiler for Agile Hardware: A Research Platform
Session 2: New Frontiers for System-Level Power Management (Invited Talks): Organizer: G. De Micheli: Chair: Luca Benini
Yung-Hsiang Lu, Stanford University
Giovanni de Micheli, Stanford University
Luca Benini, Universit? di Bologna
pp. 18
Luca Benini, Universit? di Bologna
Giuliano Castelli, Politecnico di Torino
Alberto Macii, Politecnico di Torino
Enrico Macii, Politecnico di Torino
Riccardo Scarsi, Politecnico di Torino
pp. 25
Session 3: Code Generation and Scheduling: Chair: Bob Rau
Jesús Sánchez, Universitat Polit?cnica de Catalunya
Antonio González, Universitat Polit?cnica de Catalunya
pp. 41
N.G. Busá, Philips Research Laboratories
A. Van der Werf, Philips Research Laboratories
M. Bekooij, Philips Research Laboratories
pp. 47
Chingren Lee, National Tsing-Hua University
Jenq Kuen Lee, National Tsing-Hua University
TingTing Hwang, National Tsing-Hua University
Shi-Chun Tsai, National Chi-Nan University
pp. 55
Session 4: Embedded Tutorial: Chair: Francisco Tirado
Session 5: Panel. System Level Design — Solid Advances or Survival Strategies?
Session 6: High Level and System Level Synthesis: Chair: Petru Eles
O. Peñalba, Universidad Complutense de Madrid
J. Mendías, Universidad Complutense de Madrid
M.C. Molina, Universidad Complutense de Madrid
pp. 73
Session 7: Reconfigurable Computing and Embedded Systems: Chair: Walid Najjar
Rafael Maestre, Universidad Complutense de Madrid
Milagros Fernandez, Universidad Complutense de Madrid
Fadi J. Kurdahi, University of California at Irvine
Nader Bagherzadeh, University of California at Irvine
Hartej Singh, University of California at Irvine
pp. 107
Session 8: System Level Modeling and Verification: Chair: Diederik Verkest
Fabian Wolf, Technische Universit?t Braunschweig
Rolf Ernst, Technische Universit?t Braunschweig
pp. 130
Marek Jersak, Technische Universit?t Braunschweig
Ying Cai, Technische Universit?t Braunschweig
Dirk Ziegenbein, Technische Universit?t Braunschweig
Rolf Ernst, Technische Universit?t Braunschweig
pp. 137
M. Meerwein, Robert Bosch GmbH
C. Baumgartner, Robert Bosch GmbH
T. Wieja, Robert Bosch GmbH
W. Glauert, University of Erlangen-Nuremberg
pp. 143
Session 9: Embedded Tutorial: Organizer and Chair: Peter Marwedel
Session 10: High-Level Power Estimation (InvitedTalks): Organizer and Chair: Donatella Sciuto
Lars Kruse, OFFIS Research Institute
Eike Schmidt, OFFIS Research Institute
Gerd Jochens, OFFIS Research Institute
Ansgar Stammermann, OFFIS Research Institute
Wolfgang Nebel, OFFIS Research Institute
pp. 180
C. Brandolese, Politecnico di Milano
W. Fornaciari, Politecnico di Milano
L. Pomante, Politecnico di Milano
F. Salice, Politecnico di Milano
D. Sciuto, Politecnico di Milano
pp. 187
Session 11: System Design Methodologies and Experiences: Chair: Nikil Dutt
Jeffrey Kang, Philips Research Laboratories
Albert Van der Werf, Philips Research Laboratories
Paul Lippens, Philips Research Laboratories
pp. 207
Roman L. Lysecky, University of California at Riverside
Tony D. Givargis, University of California at Riverside
Frank Vahid, University of California at Riverside and University of California at Irvine
pp. 221
Rafael Gadea, Universidad Politecnica de Valencia
Franciso Ballester, Universidad Politecnica de Valencia
Antonio Mocholí, Universidad Politecnica de Valencia
Joaquín Cerdá, Universidad Politecnica de Valencia
pp. 225
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