CSDL - Proceedings I

Steering Committee (PDF)

pp. x

Technical Program Committee (PDF)

pp. xi

Reviewers (PDF)

pp. xiii

Session 1: System Level Design Research in an Industrial Setting (Invited Talks): Organizer and Chair: Don MacMillen

IP Reuse in the System on a Chip Era (Abstract)

Warren Savage, Synopsys Inc.

John Chilton, Synopsys Inc.

Raul Camposano, Synopsys Inc.

pp. 2

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YAML: A Tool for Hardware Design Visualization and Capture (Abstract)

Vivek Sinha, University of California at Irvine

Frederic Doucet, University of California at Irvine

Chuck Siska, University of California at Irvine

Rajesh Gupta, University of California at Irvine

Stan Liao, Synopsys Inc.

Abhijit Ghosh, Synopsys Inc.

pp. 9

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The Nimble Compiler for Agile Hardware: A Research Platform

Session 2: New Frontiers for System-Level Power Management (Invited Talks): Organizer: G. De Micheli: Chair: Luca Benini

Requester-Aware Power Reduction (Abstract)

Yung-Hsiang Lu, Stanford University

Giovanni de Micheli, Stanford University

Luca Benini, Universit? di Bologna

pp. 18

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Battery-Driven Dynamic Power Management of Portable Systems (Abstract)

Luca Benini, Universit? di Bologna

Giuliano Castelli, Politecnico di Torino

Alberto Macii, Politecnico di Torino

Enrico Macii, Politecnico di Torino

Riccardo Scarsi, Politecnico di Torino

pp. 25

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The Power Managing OS Meets a Thermally Aware Processor

Session 3: Code Generation and Scheduling: Chair: Bob Rau

FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors (Abstract)

Cagdas Akturan, University of Texas at Austin

Margarida F. Jacome, University of Texas at Austin

pp. 34

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Instruction Scheduling for Clustered VLIW Architectures (Abstract)

Jesús Sánchez, Universitat Polit?cnica de Catalunya

Antonio González, Universitat Polit?cnica de Catalunya

pp. 41

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Scheduling Coarse-Grain Operations for VLIW Processors (Abstract)

N.G. Busá, Philips Research Laboratories

A. Van der Werf, Philips Research Laboratories

M. Bekooij, Philips Research Laboratories

pp. 47

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Compiler Optimization on Instruction Scheduling for Low Power (Abstract)

Chingren Lee, National Tsing-Hua University

Jenq Kuen Lee, National Tsing-Hua University

TingTing Hwang, National Tsing-Hua University

Shi-Chun Tsai, National Chi-Nan University

pp. 55

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Session 4: Embedded Tutorial: Chair: Francisco Tirado

Architectures for One Billion of Transistors (PDF)

M. Valero

pp. 62

Hierarchical Conditional Dependency Graphs as a Unifying Design Representation in the CODESIS High-Level Synthesis System (Abstract)

Session 5: Panel. System Level Design — Solid Advances or Survival Strategies?

Session 6: High Level and System Level Synthesis: Chair: Petru Eles

Apostolos A. Kountouris, Mitsubishi Electric ITE

Christophe Wolinski, Universitaire de Beaulieu

pp. 66

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Execution Condition Analysis in High Level Synthesis: A Unified Approach (Abstract)

O. Peñalba, Universidad Complutense de Madrid

J. Mendías, Universidad Complutense de Madrid

M.C. Molina, Universidad Complutense de Madrid

pp. 73

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Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design (Abstract)

Hyunuk Jung, Seoul National University

Kangnyoung Lee, Seoul National University

Soonhoi Ha, Seoul National University

pp. 79

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Efficient Integration of Behavioral Synthesis with Existing Design Flows (Abstract)

W.O. Cesário, TIMA Laboratory

A.A. Jerraya, TIMA Laboratory

Z. Sugar, Arexsys

I. Moussa, Arexsys

pp. 85

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A Joint Power/Performance Optimization Algorithm for Multiprocessor Systems Using a Period Graph Construct (Abstract)

Neal K. Bambha, University of Maryland at College Park

Shuvra S. Bhattacharyya, University of Maryland at College Park

pp. 91

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Session 7: Reconfigurable Computing and Embedded Systems: Chair: Walid Najjar

Run-Time HW/SW Codesign for Discrete Event Systems Using Dynamically Reconfigurable Architectures (Abstract)

Juanjo Noguera, University Aut?noma de Barcelona

Rosa M. Badía, University Polit?cnica de Catalunya

pp. 100

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Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization (Abstract)

Rafael Maestre, Universidad Complutense de Madrid

Milagros Fernandez, Universidad Complutense de Madrid

Fadi J. Kurdahi, University of California at Irvine

Nader Bagherzadeh, University of California at Irvine

Hartej Singh, University of California at Irvine

pp. 107

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Systematic Data Reuse Exploration Methodology for Irregular Access Patterns (Abstract)

Tanja Van Achteren, K.U.Leuven

Rudy Lauwereins, K.U.Leuven

Francky Catthoor, IMEC

pp. 115

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Conditional Scheduling for Embedded Systems Using Genetic List Scheduling (Abstract)

Martin Grajcar, University of Passau

pp. 123

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Session 8: System Level Modeling and Verification: Chair: Diederik Verkest

Intervals in Software Execution Cost Analysis (Abstract)

Fabian Wolf, Technische Universit?t Braunschweig

Rolf Ernst, Technische Universit?t Braunschweig

pp. 130

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A Transformational Approach to Constraint Relaxation of a Time-Driven Simulation Model (Abstract)

Marek Jersak, Technische Universit?t Braunschweig

Ying Cai, Technische Universit?t Braunschweig

Dirk Ziegenbein, Technische Universit?t Braunschweig

Rolf Ernst, Technische Universit?t Braunschweig

pp. 137

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Embedded Systems Verification with FPGA-Enhanced In-Circuit Emulator (Abstract)

M. Meerwein, Robert Bosch GmbH

C. Baumgartner, Robert Bosch GmbH

T. Wieja, Robert Bosch GmbH

W. Glauert, University of Erlangen-Nuremberg

pp. 143

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Verification of Embedded Systems Using a Petri Net Based Representation (Abstract)

Luis Alejandro Cortés, Link?ping University

Petru Eles, Link?ping University

Zebo Peng, Link?ping University

pp. 149

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SDL as a System Level Specification Language for Application-Specific Hardware in a Rapid Prototyping Environment (Abstract)

Annette Muth, Technische Universit?t M?nchen

Georg Färber, Technische Universit?t M?nchen

pp. 157

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Instruction-Based System-Level Power Evaluation of System-on-a-Chip Peripheral Cores (Abstract)

Tony D. Givargis, University of California at Riverside

Frank Vahid, University of California at Riverside

Jörg Henkel, NEC USA

pp. 163

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Session 9: Embedded Tutorial: Organizer and Chair: Peter Marwedel

Embedded Java (PDF)

W. Rosenstiel

pp. 172

Code Generation for Embedded Processors (Abstract)

Rainer Leupers, University of Dortmund

pp. 173

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Session 10: High-Level Power Estimation (InvitedTalks): Organizer and Chair: Donatella Sciuto

Lower Bound Estimation for Low Power High-Level Synthesis (Abstract)

Lars Kruse, OFFIS Research Institute

Eike Schmidt, OFFIS Research Institute

Gerd Jochens, OFFIS Research Institute

Ansgar Stammermann, OFFIS Research Institute

Wolfgang Nebel, OFFIS Research Institute

pp. 180

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A Multi-Level Strategy for Software Power Estimation (Abstract)

C. Brandolese, Politecnico di Milano

W. Fornaciari, Politecnico di Milano

L. Pomante, Politecnico di Milano

F. Salice, Politecnico di Milano

D. Sciuto, Politecnico di Milano

pp. 187

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Source Code Optimization and Profiling of Energy Consumption in Embedded Systems (Abstract)

Tajana ?imunic, Stanford University

Giovanni de Micheli, Stanford University

Luca Benini, University of Bologna

Mat Hans, HP Labs

pp. 193

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Session 11: System Design Methodologies and Experiences: Chair: Nikil Dutt

Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs (Abstract)

Erik Brockmeyer, IMEC

Arnout Vandecappelle, IMEC

Sven Wuytack, IMEC

Francky Catthoor, IMEC and Katholieke University Leuven

pp. 200

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Mapping Array Communication onto FIFO Communication - Towards an Implementation (Abstract)

Jeffrey Kang, Philips Research Laboratories

Albert Van der Werf, Philips Research Laboratories

Paul Lippens, Philips Research Laboratories

pp. 207

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Hardware Synthesis from SPDF Representation for Multimedia Applications (Abstract)

Chanik Park, Seoul National University

Soonhoi Ha, Seoul National University

pp. 215

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Experiments with the Peripheral Virtual Component Interface (Abstract)

Roman L. Lysecky, University of California at Riverside

Tony D. Givargis, University of California at Riverside

Frank Vahid, University of California at Riverside and University of California at Irvine

pp. 221

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Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation (Abstract)

Rafael Gadea, Universidad Politecnica de Valencia

Franciso Ballester, Universidad Politecnica de Valencia

Antonio Mocholí, Universidad Politecnica de Valencia

Joaquín Cerdá, Universidad Politecnica de Valencia

pp. 225

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Index of Authors (PDF)

pp. 231