Message from the Program

Steering Committee (PDF)

pp. x

Technical Program Committee (PDF)

pp. xi

Session 1: Invited Talks

Design of a Set-Top Box System on a Chip (Abstract)

Eric Foster, IBM Research

pp. 2

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On the Rapid Prototyping and Design of a Wireless Communication System on a Chip (Abstract)

Brian Kelley, Motorola Incorporated

pp. 3

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Session 2: Embedded Tutorial: Java Compilation Technology

Embedded Java: Techniques and Applications (Abstract)

Brian Barry John Duimovich, Object Technology International Incorporated

pp. 6

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Panel: System-Level Design: Designers' Wish List vs. Reality

System-Level Design: Designers' Wish List vs. Reality (Abstract)

Daniel Gajski, University of California at Irvine

Reinaldo Bergamaschi, IBM T. J. Watson Research Center

pp. 8

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Session 3: Invited Talk

Micro Electromechanical Systems (MEMS): Miniaturization Beyond Microelectronics (Abstract)

Nadim Maluf, Lucas NovaSensor and Stanford University

pp. 10

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Session 4: Embedded Tutorial

Middleware Techniques and Optimizations for Real-Time, Embedded Systems (Abstract)

Douglas C. Schmidt, University of California at Irvine

pp. 12

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Session 5: Real-Time and Low Power System Design

Event-Driven Power Management of Portable Systems (Abstract)

Tajana Simunic, Stanford University

Giovanni de Micheli, Stanford University

Luca Benini, Universit? di Bologna

pp. 18

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Real-Time Task Scheduling for a Variable Voltage Processor (Abstract)

Takanori Okuma, Kyushu University

Tohru Ishihara, Kyushu University

Hiroto Yasuura, Kyushu University

pp. 24

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Path-Based Edge Activation for Dynamic Run-Time Scheduling (Abstract)

Vincent J. Mooney Iii, Georgia Institute of Technology

pp. 30

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Session 6: Performance Issues in System Design

Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs (Abstract)

Jens Horstmannshoff, Integrated Signal Processing Systems

Heinrich Meyr, Integrated Signal Processing Systems

pp. 38

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RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions (Abstract)

Peter Grun, University of California at Irvine

Ashok Halambi, University of California at Irvine

Nikil Dutt, University of California at Irvine

Alex Nicolau, University of California at Irvine

pp. 44

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Pre-Fetching for Improved Core Interfacing (Abstract)

Roman Lysecky, University of California at Riverside

Frank Vahid, University of California at Riverside

Tony Givargis, University of California at Riverside

Rilesh Patel, University of California at Riverside

pp. 51

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Compressed Code Execution on DSP Architectures (Abstract)

Paulo Centoducatte, IC-UNICAMP

Guido Araujo, IC-UNICAMP

Ricardo Pannain, II-PUC Campinas

pp. 56

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Session 7: Memory Design for Embedded Systems

Loop Scheduling and Partitions for Hiding Memory Latencies (Abstract)

Fei Chen, University of Notre Dame

Edwin Hsing-Mean Sha, University of Notre Dame

pp. 64

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Loop Alignment for Memory Accesses Optimization (Abstract)

Antoine Fraboulet, ENS Lyon

Guillaume Huard, ENS Lyon

Anne Mignotte, ENS Lyon

pp. 71

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A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications (Abstract)

Praveen K. Murthy, Angeles Design Systems

Shuvra S. Bhattacharyya, University of Maryland

pp. 78

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Exploration and Synthesis of Dynamic Data Sets in Telecom Network Applications (Abstract)

Ch. Ykman-Couvreur, IMEC

J. Lambrecht, IMEC

D. Verkest, IMEC

F. Catthoor, IMEC and Katholieke University of Leuven

H. de Man, IMEC and Katholieke University of Leuven

pp. 85

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Session 8: Architectural Synthesis

A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters (Abstract)

Khurram Muhammad, Texas Instruments Incorporated

Kaushik Roy, Purdue University

pp. 94

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Efficient Scheduling of DSP Code on Processors with Distributed Register Files (Abstract)

Bart Mesman, Philips Research Laboratories

Carlos A. Alba Pinto, Eindhoven University of Technology

Koen Van Eijk, Eindhoven University of Technology

pp. 100

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Automatic Architectural Synthesis of VLIW and EPIC Processors (Abstract)

Shail Aditya, Hewlett-Packard Laboratories

B. Ramakrishna Rau, Hewlett-Packard Laboratories

Vinod Kathail, Hewlett-Packard Laboratories

pp. 107

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Bit-Width Selection for Data-Path Implementations (Abstract)

Carlos Carreras, Universidad Polit?cnica de Madrid

Juan A. López, Universidad Polit?cnica de Madrid

Octavio Nieto-Taladriz, Universidad Polit?cnica de Madrid

pp. 114

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Session 9: System Design Methodologies

Catalyst: A DSIP Design Flow Development in Industry (Abstract)

W. de Rammelaere, Motorola SPS

K. Eckert, Motorola SPS

E. Hilkens, Motorola SPS

T. Lawell, Motorola SPS

R. McGarity, Motorola SPS

P. Le Moenner, Motorola SPS

F. Steininger, Motorola SPS

pp. 122

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System Synthesis of Synchronous Multimedia Applications (Abstract)

Gang Qu, University of California at Los Angeles

Malena Mesarina, University of California at Los Angeles

Miodrag Potkonjak, University of California at Los Angeles

pp. 128

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A Framework for Scheduling and Context Allocation in Reconfigurable Computing (Abstract)

R. Maestre, Universidad Complutense

M. Fernandez, Universidad Complutense

R. Hermida, Universidad Complutense

N. Bagherzadeh, University of California at Irvine

pp. 134

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Index of Authors (PDF)

pp. 141