Message from the Program Chair

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Invited Talks (Abstract)

pp. ix

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Steering Committee (Abstract)

pp. x

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Technical Program Committee (Abstract)

pp. xi

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Reviewers (Abstract)

pp. xii

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Invited Talk

Is IP Business Hype or Reality?

Session 1: Code Generation and Optimization Issues

A Uniform Optimization Technique for Offset Assignment Problems (Abstract)

Rainer Leupers

Fabian David

pp. 3

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Code Generation for Compiled Bit-True Simulation of DSP Applications (Abstract)

pp. 9

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Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture (Abstract)

Wei-Kai Cheng

Youn-Long Lin

pp. 15

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Issues in Embedded DRAM Development and Applications (Abstract)

D. Keitel-Schulz

N. Wehn

pp. 23

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Session 2: IP Reuse and Language

A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools (Abstract)

Chuck Siska

pp. 31

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A. Sangiovanni-Vincentelli

Intellectual Property Re-use in Embedded System Co-design: An Industrial Case Study (Abstract)

pp. 37

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Incorporating Cores into System-Level Specification (Abstract)

Frank Vahid

Tony Givargis

pp. 43

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Poster Presentations

HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation (Abstract)

Rainer Leupers

pp. 51

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False Path Analysis Based on a Hierarchical Control Representation (Abstract)

Apostolos A. Kountouris

Christophe Wolinski

pp. 55

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Resource Constrained Modulo Scheduling with Global Resource Sharing (Abstract)

Christoph J?schke

Rainer Laur

pp. 60

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Statistical Performance-Driven Module Binding in High-Level Synthesis (Abstract)

pp. 66

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Concurrent Error Detection at Architectural Level (Abstract)

pp. 72

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Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System (Abstract)

Yin-Tsung Hwang

Yuan-Hung Wang

pp. 76

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Processor Architectures and Compilers for Systems on Chips

Session 3: Application-Specific Synthesis Techniques

Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution (Abstract)

Allan Rae

Sri Parameswaran

pp. 83

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Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media Applications (Abstract)

pp. 89

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Data-Path Synthesis of VLIW Video Signal Processors (Abstract)

Zhao Wu

Wayne Wolf

pp. 96

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Session 4: Synchronization and Interface Issues

Synchronization Detection for Multi-Process Hierarchical Synthesis (Abstract)

pp. 105

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Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign (Abstract)

Peter Voigt Knudsen

Jan Madsen

pp. 111

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Interface Exploration for Reduced Power in Core-Based Systems (Abstract)

Tony Givargis

Frank Vahid

pp. 117

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Session 5: Instruction Encoding and Software Synthesis Techniques

Instruction Encoding Techniques for Area Minimization of Instruction ROM (Abstract)

pp. 125

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Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation (Abstract)

Ing-Jer Huang

Ping-Huei Xie

pp. 131

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Memory Efficient Software Synthesis from Dataflow Graph (Abstract)

pp. 137

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Session 6: Partitioning and Scheduling Techniques

A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems (Abstract)

Karam S. Chatha

Ranga Vemuri

pp. 145

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A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes (Abstract)

Frank Vahid

pp. 152

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Fine Grain Incremental Rescheduling Via Architectural Retiming (Abstract)

Soha Hassoun

pp. 158

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Author Index (Abstract)

pp. 164

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