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10th International Symposium on System Synthesis (ISSS '97)
Antwerp, BELGIUM
September 17-September 19
ISBN: 0-8186-7949-2
Table of Contents
Session 1: Formal Specification and Validation
Panel Discussion: Where is Fast Prototyping Heading?
Session 2: Fast Prototyping and Code Generation
A. Hein, ESAT/ACCA Laboratory
J. Dalcolmo, ESAT/ACCA Laboratory
P. Le Corre, ESAT/ACCA Laboratory
R. Lauwereins, ESAT/ACCA Laboratory
M. Ade', ESAT/ACCA Laboratory
pp. 26
Bart Mesman, Philips Research laboratories
Marino T.J. Strik, Philips Research laboratories
Adwin H. Timmer, Philips Research laboratories
Jef L. Van Meerbergen, Philips Research laboratories
Jochen A.G. Jess, Design Automation Section Eindhoven University of Technology
pp. 33
Session 3: Novel Compilation and Optimization Issues
Anne Mignotte, Laboratoire de l'Informatique du Parall?lisme
Olivier Peyran, Laboratoire de l'Informatique du Parall?lisme
pp. 58
Session 4: Memory Management Issues
Preeti Ranjan Panda, University of California, Irvine
Nikil D. Dutt, University of California, Irvine
Alexandru Nicolau, University of California, Irvine
pp. 90
Panel Discussion: How Will Memory Issues Impact Synthesis for Embedded Systems-on-Silicon?
Session 5: System-Level Synthesis and Design
Session 6: HW/SW Specification and Debugging
Gernot Koch, Forschungszentrum Informatik
Udo Kebschull, Forschungszentrum Informatik
Wolfgang Rosenstiel, University of Tuebingen
pp. 120
Chih-Tung Chen, Unified Design System Laboratory Motorola, Inc.
Kayhan Kucukcakar, Unified Design System Laboratory Motorola, Inc.
pp. 134
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