CSDL - Proceedings I

Conference Committee (PDF)

pp. viii

Technical Program Committee (PDF)

pp. ix

Reviewers (PDF)

pp. xi

Session 1: System-Level Synthesis I

System-Level Synthesis of Application Specific Systems using A* Search and Generalized Force-Directed Heuristics (Abstract)

Chunho Lee, University of California, Los Angeles

Miodrag Potkonjak, University of California, Los Angeles

Wayne Wolf, Princeton University

pp. 2

PDF

Toward a Practical Methodology for Completely Characterizing the Optimal Design Space (Abstract)

Stephen A. Blythe, Rensselaer Polytechnic Institute

Robert A. Walker, Kent State University

pp. 8

PDF

Grammar-based Hardware Synthesis of Data Communication Protocols (Abstract)

Johnny OEberg, Institute of Technology

Anshul Kumar, Institute of Technology

Ahmed Royal, Institute of Technology

pp. 14

PDF

ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures (Abstract)

pp. 20

PDF

Breakpoints and Breakpoint Detection in Source Level Emulation (Abstract)

Gernot Koch, Forschungszentrum Informatik (FZI)

Udo Kebschull, Forschungszentrum Informatik (FZI)

Wolfgang Rosenstiel, FZI and University of Tubingen

pp. 26

PDF

Session 2: High-Level Synthesis

Layout-driven RTL binding techniques for high-level synthesis (Abstract)

Min Xu, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA

F.J. Kurdahi, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA

pp. 33

PDF

Eliminating false loops caused by sharing in control path (Abstract)

A. Su, Dept. of Comput. Sci., California Univ., Riverside, CA, USA

Ta-Yung Liu, Dept. of Comput. Sci., California Univ., Riverside, CA, USA

Yu-Chin Hsu, Dept. of Comput. Sci., California Univ., Riverside, CA, USA

M.T.-C. Lee, Dept. of Comput. Sci., California Univ., Riverside, CA, USA

pp. 39

PDF

An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions (Abstract)

Authors: Michael Muench, Darmstadt University of Technology

Manfred Glesner, Darmstadt University of Technology

Norbert Wehn, Siemens AG

pp. 45

PDF

A Constructive Method for Exploiting Code Motion (Abstract)

Luiz C. V. dos Santos, Eindhoven University of Technology

M.J.M. Heijligers, Eindhoven University of Technology

C.A.J. Van Eijk, Eindhoven University of Technology

J.T.J. Van Eijndhoven, Eindhoven University of Technology

J.A.G. Jess, Eindhoven University of Technology

pp. 51

PDF

Synthesis of low-power selectively-clocked systems from high-level specification (Abstract)

L. Benini, Stanford University

P. Vuillod, Stanford University

G. de Micheli, Stanford University

Claudionor Coelho, University of Minas Gerais (UFMG)

pp. 57

PDF

Session 3: Hardware/Software Codesign

Bus-Based Communication Synthesis on System-Level (Abstract)

Michael Gasteier, Darmstadt University of Technology

Manfred Glesner, Darmstadt University of Technology

pp. 65

PDF

Hardware/Software Partitioning with Iterative Improvement Heuristics (Abstract)

Petru Eles, Linkoping University

Zebo Peng1, Linkoping University

Krzysztof Kuchcinski, Linkoping University

Alexa Doboli, Technical University of Timisoara

pp. 71

PDF

The use of a virtual instruction set for the software synthesis of Hw/Sw embedded systems (Abstract)

A. Balboni, ITALTEL-SIT, Milan, Italy

W. Fornaciari, ITALTEL-SIT, Milan, Italy

D. Sciuto, ITALTEL-SIT, Milan, Italy

M. Vincenzi, ITALTEL-SIT, Milan, Italy

pp. 77

PDF

A Codesign Experiment in Acoustic Echo Cancellation: GMDFa (Abstract)

Frederic Rousseau, Universite d'Evry

pp. 83

PDF

Session 4: Programmable Processor Based Design and Synthesis

Memory Organization for Improved Data Cache Performance in Embedded Processors (Abstract)

Preeti Ranjan Panda, University of California

Nikil D. Dutt, University of California

Alexandru Nicolau, University of California

pp. 90

PDF

Size-Constrained Code Placement for Cache Miss Rate Reduction (Abstract)

H. Tomiyama

H. Yasuura

pp. 96

PDF

Instruction Set Design and Optimizations for Address Computation in DSP Architectures (Abstract)

pp. 102

PDF

DSP processor/compiler co-design: a quantitative approach (Abstract)

V. Zivojnovic, Integrated Syst. for Signal Process., Tech. Hochschule Aachen, Germany

S. Pees, Integrated Syst. for Signal Process., Tech. Hochschule Aachen, Germany

C. Schlager, Integrated Syst. for Signal Process., Tech. Hochschule Aachen, Germany

M. Willems, Integrated Syst. for Signal Process., Tech. Hochschule Aachen, Germany

R. Schoenen, Integrated Syst. for Signal Process., Tech. Hochschule Aachen, Germany

H. Meyr, Integrated Syst. for Signal Process., Tech. Hochschule Aachen, Germany

pp. 108

PDF

Session 5: System-Level Synthesis II

Modeling Multicomputer Task Allocation as a Vector Packing Problem (Abstract)

James Beck, Delco Electronics Corp.

Daniel Siewiorek, Carnegie Mellon University

pp. 115

PDF

A Comparison of Functional and Structural Partitioning (Abstract)

pp. 121

PDF

Flow Graph Balancing for Minimizing the Required Memory Bandwidth (Abstract)

Sven Wuytack, IMEC

Francky Catthoor, IMEC

Gjalt de Jong, IMEC

Bill Lin, IMEC

Hugo de Man, IMEC

pp. 127

PDF

Throughput Optimization in Disk-Based Real-Time Application Specific Systems (Abstract)

Stephen Docy, University of California, Los Angeles

Inki Hong, University of California, Los Angeles

Miodrag Potkonjak, University of California, Los Angeles

pp. 133

PDF

Testability Insertion in Behavioral Descriptions (Abstract)

Frank F. Hsu, University of Illinois

Elizabeth M. Rudnick, University of Illinois

Janak H. Patel, University of Illinois

pp. 139

PDF

Index of Authors (PDF)

pp. 145