CSDL - Proceedings I

Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-xviii

Welcome Notes (PDF)

pp. xix-xx

Organizing Committee/Best Paper (PDF)

pp. xxi

Technical Subcommittee Lists (PDF)

pp. xxii-xxv

Steering/Advisory Committee (PDF)

pp. xxvi

Conference at a Glance (PDF)

pp. xxvii-xxviii

Tutorial 1: The Promise of High-?/Metal Gates-From Electronic Transport Phenomena to Emerging Device/Circuit Applications (Abstract)

K. Maitra

pp. 3

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Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies (Abstract)

Chris Kim

pp. 4

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Tutorial 3: Process Technology Development and New Design Opportunities in 3D Integration Technology (Abstract)

Robert E. Jones

pp. 5

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Tutorial 4: Robust System Design in Scaled CMOS (Abstract)

Subhasis Mitra

pp. 6

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Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve? (Abstract)

Hillary Hunter

pp. 7

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Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM) (Abstract)

Praveen Elakkumanan

pp. 8-9

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Plenary Speech 1P1: Shrinking time-to-market through global value chain integration (Abstract)

Drew Gude

pp. 15

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Plenary Speech 1P2: Bounding the Endless Verification Loop (Abstract)

Robert Hum

pp. 16-17

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A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS (Abstract)

pp. 23-29

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Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation (Abstract)

pp. 30-34

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Error Protected Data Bus Inversion Using Standard DRAM Components (Abstract)

Maurzio Skerlj

Paolo Ienne

pp. 35-42

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Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects (Abstract)

Chittarsu Raghunandan

K.S. Sainarayanan

M.B. Srinivas

pp. 43-46

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Leomar Soares da Rosa Jr.

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering (Abstract)

Tiago Muller Gil Cardoso

Felipe de Souza Marques

Renato Perez Ribas

Andre Inacio Reis

pp. 47-52

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Fast and Accurate Waveform Analysis with Current Source Models (Abstract)

pp. 53-56

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An Efficient Method for Fast Delay and SI Calculation Using Current Source Models (Abstract)

pp. 57-61

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Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model (Abstract)

Yi Wang

Xuan Zeng

Jun Tao

Hengliang Zhu

Xu Luo

Changhao Yan

Wei Cai

pp. 62-67

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Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes (Abstract)

Avijit Dutta

Abhijit Jas

pp. 68-73

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Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths (Abstract)

Yu Wang

pp. 74-77

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IR Drop Reduction via a Flip-Flop Resynthesis Technique (Abstract)

pp. 78-83

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Noise Interaction Between Power Distribution Grids and Substrate (Abstract)

pp. 84-89

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Luncheon Keynote Speech (Abstract)

Antun Domic

pp. 90-91

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Fundamental Data Retention Limits in SRAM Standby Experimental Results (Abstract)

pp. 92-97

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Quality of a Bit (QoB): A New Concept in Dependable SRAM (Abstract)

pp. 98-102

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Cache Design for Low Power and High Yield (Abstract)

pp. 103-107

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Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations (Abstract)

Xin Li

pp. 108-113

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High Output Resistance and Wide Swing Voltage Charge Pump Circuit (Abstract)

Tian Xia

Stephen Wyatt

pp. 114-117

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Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses (Abstract)

Krishnan Sundaresan

Nihar R. Mahapatra

pp. 118-122

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A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design (Abstract)

Saravanan Ramamoorthy

Haibo Wang

Sarma Vrudhula

pp. 123-126

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Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation (Abstract)

Joseph F. Ryan

Benton H. Calhoun

pp. 127-132

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Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM (Abstract)

pp. 133-136

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Accurate Temperature Estimation for Efficient Thermal Management (Abstract)

Shervin Sharifi

ChunChen Liu

Tajana Simunic Rosing

pp. 137-142

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Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic (Abstract)

Kumar Yelamarthi

Chien-In Henry Chen

pp. 143-147

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Seyed-Abdollah Aftabjahani

Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis (Abstract)

Linda S. Milor

pp. 148-151

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A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors (Abstract)

pp. 152-155

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Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations (Abstract)

Lin Xie

Azadeh Davoodi

pp. 156-161

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Variation Aware Spline Center and Range Modeling for Analog Circuit Performance (Abstract)

pp. 162-167

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High-Quality Circuit Synthesis for Modern Technologies (Abstract)

Lech Jozwiak

Artur Chojnacki

Aleksander Slusarczyk

pp. 168-173

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ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis (Abstract)

Saraju P. Mohanty

pp. 174-177

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Improving the Efficiency of Power Management Techniques by Using Bayesian Classification (Abstract)

Hwisung Jung

Massoud Pedram

pp. 178-183

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An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems (Abstract)

pp. 184-189

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Constant Rate Dataflow Model with Intermediate Ports for Efficient Code Synthesis with Top-Down Design and Dynamic Behavior (Abstract)

Hyunok Oh

pp. 190-193

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Thermal-Aware IR Drop Analysis in Large Power Grid (Abstract)

Yu Zhong

Martin D.F. Wong

pp. 194-199

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A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations (Abstract)

pp. 200-206

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Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model (Abstract)

pp. 207-212

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Characterization of Standard Cells for Intra-Cell Mismatch Variations (Abstract)

Savithri Sundareswaran

pp. 213-219

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Full-Chip Leakage Verification for Manufacturing Considering Process Variations (Abstract)

Tao Li

Zhiping Yu

pp. 220-223

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Processor Verification with hwBugHunt (Abstract)

Sangeetha Sudhakrishnan

Liying Su

Jose Renau

pp. 224-229

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Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions (Abstract)

pp. 230-235

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Efficient Selection of Observation Points for Functional Tests (Abstract)

pp. 236-241

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A Novel Test Generation Methodology for Adaptive Diagnosis (Abstract)

pp. 242-245

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Malgorzata Marek-Sadowska

Timing-Aware Multiple-Delay-Fault Diagnosis (Abstract)

Vishal J. Mehta

Kun-Han Tsai

Janusz Rajski

pp. 246-253

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A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs (Abstract)

pp. 257-260

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Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates (Abstract)

pp. 261-266

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A Statistic-Based Approach to Testability Analysis (Abstract)

pp. 267-270

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Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes (Abstract)

Feng Liu

Jin He

Yue Fu

pp. 271-276

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On the Feasibility of Obtaining a Globally Optimal Floorplanning for an L-shaped Layout Problem (Abstract)

pp. 277-282

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Architecting for Physical Verification Performance and Scaling (Abstract)

John Ferguson

Robert Todd

pp. 283-288

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Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm (Abstract)

pp. 289-292

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CMOS Based Low Cost Temperature Sensor (Abstract)

Neehar Jandhyala

Lili He

Morris Jones

pp. 293-296

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An SSO Based Methodology for EM Emission Estimation from SoCs (Abstract)

pp. 297-300

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Fast Timing Update under the Effect of IR Drop (Abstract)

Muzhou Shao

pp. 301-304

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Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations (Abstract)

pp. 305-310

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Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations (Abstract)

Sherif A. Tawfik

Volkan Kursun

pp. 311-316

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A Low Energy Two-Step Successive Approximation Algorithm for ADC Design (Abstract)

Ricky Yiu-kee Choi

Chi-ying Tsui

pp. 317-320

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Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration (Abstract)

pp. 321-324

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Process Variability Analysis in DSM Through Statistical Simulations and its Implications to Design Methodologies (Abstract)

Srinivasa R STG

Jandhyala Srivatsava

Narahari Tondamuthuru R

pp. 325-329

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Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design (Abstract)

pp. 330-333

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Evaluation of the PTSI Crosstalk Noise Analysis Tool and Development of an Automated Spice Correlation Suite to Enable Accuracy Validation (Abstract)

pp. 334-337

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Hotspot Based Yield Prediction with Consideration of Correlations (Abstract)

Qing Su

Charles Chiang

Jamil Kawa

pp. 338-343

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A Randomized Greedy Algorithm for the Pattern Fill Problem for DFM Applications (Abstract)

Maharaj Mukherjee

Kanad Chakraborty

pp. 344-347

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A Passive 915 MHz UHF RFID Tag (Abstract)

pp. 348-351

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Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner (Abstract)

Jae-Seok Yang

Andrew R. Neureuther

pp. 352-356

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DFM Based Detailed Routing Algorithm for ECP and CMP (Abstract)

pp. 357-360

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Instruction Scheduling for Variation-Originated Variable Latencies (Abstract)

Toshinori Sato

Shingo Watanabe

pp. 361-364

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Hotspot Prevention Using CMP Model in Design Implementation Flow (Abstract)

Li Song

pp. 365-368

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The Statistical Failure Analysis for the Design of Robust SRAM in Nano-Scale Era (Abstract)

pp. 369-372

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Harindranath Parameswaran

Computation of Waveform Sensitivity Using Geometric Transforms for SSTA (Abstract)

Ratnakar Goyal

Sachin Shrivastava

pp. 373-378

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On Efficient and Robust Constraint Generation for Practical Layout Legalization (Abstract)

Sambuddha Bhattacharya

Shabbir H. Batterywala

Subramanian Rajagopalan

Hi-Keung Tony Ma

Narendra V. Shenoy

pp. 379-384

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Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family (Abstract)

Charbel J. Akl

Magdy A. Bayoumi

pp. 385-390

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Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures (Abstract)

pp. 391-395

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Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs (Abstract)

pp. 396-400

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Analytical Noise-Rejection Model Based on Short Channel MOSFET (Abstract)

Vinay Jain

Payman Zarkesh-Ha

pp. 401-406

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A High-Performance Bus Architecture for Strongly Coupled Interconnects (Abstract)

Michael N. Skoufis

Kedar Karmarkar

Themistoklis Haniotakis

Spyros Tragoudas

pp. 407-410

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A Fully-Integrated 2.4 GHz??Mismatch-Controllable RF Front-end Test Platform in 0.18?m CMOS (Abstract)

Zahra Sadat Ebadi

Resve Saleh

pp. 411-416

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A Holistic Approach to SoC Verification (Abstract)

pp. 417-422

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A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel?s Test Chips (Abstract)

Nathaniel August

pp. 423-428

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Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium Devices (Abstract)

pp. 429-432

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Verification of IP-Core Based SoC's (Abstract)

Anil Deshpande

pp. 433-436

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Innovative Test Solutions for Pin-Limited Microcontrollers (Abstract)

Matthew G. Stout

Kenneth P. Tumin

pp. 437-440

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XStatic: A Simulation Based ESD Verification and Debug Environment (Abstract)

Ganesh R. Shamnur

Rajesh R. Berigei

pp. 441-444

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Harindranath Parameswaran

Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping (Abstract)

Sachin Shrivastava

pp. 445-449

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Cell Swapping Based Migration Methodology for Analog and Custom Layouts (Abstract)

Shabbir H. Batterywala

Sambuddha Bhattacharya

Subramanian Rajagopalan

Hi-Keung Tony Ma

Narendra V. Shenoy

pp. 450-455

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A Knowledge-Based Tool for Generating and Verifying Hardware-Ready Embedded Memory Models (Abstract)

Paul Pao-Fang Cheng

pp. 456-459

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System Verilog for Quality of Results (QoR) (Abstract)

Ravi Surepeddi

pp. 460-464

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Power Delivery System: Sufficiency, Efficiency, and Stability (Abstract)

Zhen Mu

pp. 465-469

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Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability (Abstract)

pp. 470-475

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Clock Skew Analysis via Vector Fitting in Frequency Domain (Abstract)

pp. 476-479

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An Approach for a Comprehensive QA Methodology for the PDKs (Abstract)

pp. 480-483

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Strategies for Quality CAD PDKs (Abstract)

pp. 484-487

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Variability Analysis for sub-100nm PD/SOI Sense-Amplifier (Abstract)

pp. 488-491

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Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework (Abstract)

pp. 492-497

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Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics (Abstract)

Rasit Onur Topaloglu

pp. 498-501

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A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design (Abstract)

Saurabh Sinha

Asha Balijepalli

pp. 502-507

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Adaptive Branch and Bound Using SAT to Estimate False Crosstalk (Abstract)

pp. 508-513

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Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing (Abstract)

pp. 514-519

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Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution (Abstract)

pp. 520-525

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A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs (Abstract)

pp. 526-530

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Study on the Si-Ge Nanowire MOSFETs with the Core-Shell Structure (Abstract)

Yue Fu

Jin He

pp. 531-536

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Elastic Timing Scheme for Energy-Efficient and Robust Performance (Abstract)

pp. 537-542

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Statistical Models and Frequency-Dependent Corner Models for Passive Devices (Abstract)

Ning Lu

pp. 543-548

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A Thermal-Friendly Load-Balancing Technique for Multi-Core Processors (Abstract)

Enric Musoll

pp. 549-552

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Analytical Model for the Propagation Delay of Through Silicon Vias (Abstract)

pp. 553-556

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Sampling Error Estimation in High-Speed Sampling Systems Introduced by the Presence of Phase Noise in the Sampling Clock (Abstract)

Salam D. Marougi

pp. 557-563

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A QoS Scheduler for Real-Time Embedded Systems (Abstract)

pp. 564-567

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FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver (Abstract)

pp. 568-571

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A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks (Abstract)

Jeff Mueller

Resve Saleh

pp. 572-577

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Plenary Speech 2P1: Consumerization of Electronics and Nanometer Technologies: Implications for Manufacturing Test (Abstract)

Sanjiv Taneja

pp. 585

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Plenary Speech 2P2: Statistical Techniques to Achieve Robustness and Quality (Abstract)

Chandu Visweswariah

pp. 586

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Plenary Speech 2P3: The Greening of The SoC - How Electrical Engineers Will Save The World (Abstract)

Rich Goldman

pp. 587-588

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System-in-Package Technology: Opportunities and Challenges (Abstract)

Anna Fontanelli

pp. 589-593

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Printed Circuit Board Assembly Test Process and Design for Testability (Abstract)

Thao Nguyen

Navid Rezvani

pp. 594-599

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Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages (Abstract)

pp. 600-603

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An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign (Abstract)

Ming-Fang Lai

Hung-Ming Chen

pp. 604-607

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Santhosh Coimbatore Vaidyanathan

Techniques for Early Package Closure in System-in-Packages (Abstract)

Amit Mangesh Brahme

Jairam Sukumar

pp. 608-613

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Fast Shape Optimization of Metallization Patterns for DMOS Based Driver (Abstract)

Bo Yang

Shigetoshi Nakatake

Hiroshi Murata

pp. 617-620

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MAISE: An Interconnect Simulation Engine for Timing and Noise Analysis (Abstract)

Frank Liu

Peter Feldmann

pp. 621-626

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Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding (Abstract)

Peng Li

pp. 627-632

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Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures (Abstract)

pp. 633-636

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2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions (Abstract)

Dan Zhu

Tun Li

Yang Guo

Si-kun Li

pp. 637-642

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Automated Standard Cell Library Analysis for Improved Defect Modeling (Abstract)

Jason G. Brown

R.D. (Shawn) Blanton

pp. 643-648

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A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test (Abstract)

Ho Fai Ko

Nicola Nicolici

pp. 649-654

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Finite-Point Gate Model for Fast Timing and Power Analysis (Abstract)

Dinesh Ganesan

Alex Mitev

Janet Wang

pp. 657-662

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Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach (Abstract)

pp. 663-669

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Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces (Abstract)

Hai Lan

Ralf Schmitt

Chuck Yuan

pp. 670-675

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Practical Clock Tree Robustness Signoff Metrics (Abstract)

pp. 676-679

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Hierarchical Soft Error Estimation Tool (HSEET) (Abstract)

Y. Xie

K. Unlu

pp. 680-683

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Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM) (Abstract)

Hai Li

pp. 684-690

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Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect (Abstract)

Arthur Nieuwoudt

Yehia Massoud

pp. 691-696

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Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar (Abstract)

Rajat Subhra Chakraborty

Swarup Bhunia

pp. 697-701

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Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield (Abstract)

pp. 702-707

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High Resolution Read-Out Circuit for DNA Label-Free Detection System (Abstract)

Daniela De Venuto

Bruno Ricc?

pp. 708-711

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Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation (Abstract)

Lin Xie

Azadeh Davoodi

pp. 712-717

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Characterizing Intra-Die Spatial Correlation Using Spectral Density Method (Abstract)

Jun Tao

pp. 718-723

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Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and Noise (Abstract)

pp. 724-729

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Process-Variation Statistical Modeling for VLSI Timing Analysis (Abstract)

Charlie Chung Ping Chen

pp. 730-733

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A Design Model for Random Process Variability (Abstract)

pp. 734-737

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Sri Hari Krishna Narayanan

A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm (Abstract)

Ozcan Ozturk

Mahmut Kandemir

pp. 738-743

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Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform (Abstract)

Allen C. Cheng

pp. 744-749

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Runtime Validation of Transactional Memory Systems (Abstract)

pp. 750-756

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SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems (Abstract)

Makoto Sugihara

pp. 757-762

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Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect (Abstract)

Wenping Wang

Shengqi Yang

pp. 763-768

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An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node (Abstract)

pp. 769-773

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Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation (Abstract)

Bin Zhang

Michael Orshansky

pp. 774-779

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Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems (Abstract)

pp. 780-783

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A Basis for Formal Robustness Checking (Abstract)

Goerschwin Fey

Rolf Drechsler

pp. 784-789

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Quantified Impacts of Guardband Reduction on Design Process Outcomes (Abstract)

pp. 790-797

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Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits (Abstract)

Uthman Alsaiari

Resve Saleh

pp. 798-803

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A Root-Finding Method for Assessing SRAM Stability (Abstract)

Zhuo Li

pp. 804-809

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Cellwise OPC Based on Reduced Standard Cell Library (Abstract)

Hailong Jiao

Lan Chen

pp. 810-814

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On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits (Abstract)

pp. 815-820

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Interval Based X-Masking for Scan Compression Architectures (Abstract)

Anshuman Chandra

Rohit Kapur

pp. 821-826

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Two New Methods for Accurate Test Set Relaxation via Test Set Replacement (Abstract)

Stelios Neophytou

Maria K. Michael

pp. 827-831

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Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing (Abstract)

Adam B. Kinsman

Nicola Nicolici

pp. 832-837

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A Built-in Test and Characterization Method for Circuit Marginality Related Failures (Abstract)

Alodeep Sanyal

Sandip Kundu

pp. 838-843

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On Chip Jitter Measurement through a High Accuracy TDC (Abstract)

Akhil Garg

Prashant Dubey

pp. 844-847

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Robust Analog Design for Automotive Applications by Design Centering with Safe Operating Areas (Abstract)

pp. 848-854

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Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation (Abstract)

Sherif A. Tawfik

Volkan Kursun

pp. 855-860

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Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect (Abstract)

Yu Zhou

Somnath Paul

Swarup Bhunia

pp. 861-866

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Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method (Abstract)

Zuying Luo

Sheldon X.-D. Tan

pp. 867-872

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IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization (Abstract)

pp. 873-876

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Author Index (PDF)

pp. 877-883

ISQED 2009 Call for Papers (PDF)

pp. 886-887

Roster (PDF)

pp. 888