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9th International Symposium on Quality Electronic Design (isqed 2008)
System-in-Package Technology: Opportunities and Challenges
March 17-March 19
ISBN: 978-0-7695-3117-5
| ASCII Text | x | ||
| Anna Fontanelli, "System-in-Package Technology: Opportunities and Challenges," Quality Electronic Design, International Symposium on, pp. 589-593, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008. | |||
| BibTex | x | ||
| @article{ 10.1109/ISQED.2008.63, author = {Anna Fontanelli}, title = {System-in-Package Technology: Opportunities and Challenges}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2008}, isbn = {978-0-7695-3117-5}, pages = {589-593}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.63}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Quality Electronic Design, International Symposium on TI - System-in-Package Technology: Opportunities and Challenges SN - 978-0-7695-3117-5 SP589 EP593 A1 - Anna Fontanelli, PY - 2008 KW - System in Package KW - Co-design KW - Stack KW - IO Planning VL - 0 JA - Quality Electronic Design, International Symposium on ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.63
In 2006, the leading wireless phone industry has introduced literally hundreds of new, different wireless phones, which have been manufactured in approximately 1 billion units, generating revenue of about $128B. The semiconductor revenue has been about $33B. The ASP is declining, both in the wireless phone and semiconductor industry. In order to fix that, Moore's Law is being inverted: instead of getting twice the transistors for the same cost, the wireless phones industry seeks to obtain the same number of transistors for half the cost. This is making System-on-chip (SoC) no longer a viable solution. System-in-Package (SiP) looks much more promising.Lack of EDA solutions — especially the A of automation — has so far slowed down the ramp-up of SiP. In this paper we describe the landscape and present a SiP platform solution which addresses the challenges of simplification, cost reduction, quality and reliability improvement, yet allowing exploiting the most recent advances in IC packaging.
Index Terms:
System in Package, Co-design, Stack, IO Planning
Citation:
Anna Fontanelli, "System-in-Package Technology: Opportunities and Challenges," isqed, pp.589-593, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008
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