Yield of nanometer-scale devices is increasingly challenging due to the increasing contribution of systematic defects that are affected by the product design itself. While inline inspection has been the conventional tool used to detect and isolate significant yield limiting mechanisms, there is a need to augment this information with the analysis of electrical test results obtained using electrical structural test of the finial product. The biggest challenge is employing new methods and tools that can accommodate the voluminous amount of data that can accumulate during this process. This paper describes the methods and tools required to manage the data in both time and data-volume efficiency. The described methodology includes the levels of data accumulation and the processing at the various levels; at the tester, offline pre-processing to convert the electrical failures to the specific physical circuit elements causing the fault, and then to the Yield Management System.