This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
8th International Symposium on Quality Electronic Design (ISQED'07)
Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability
San Jose, California
March 26-March 28
ISBN: 0-7695-2795-7
Benoit Dubois, Institut d'Electronique du Solide et des Systemes, France
Jean-Baptiste Kammerer, Institut d'Electronique du Solide et des Systemes, France
Luc Hebrard, Institut d'Electronique du Solide et des Systemes, France
Francis Braun, Institut d'Electronique du Solide et des Systemes, France
A CMOS transistor ageing analytical model is presented and the procedure that allows to extract its parameters is proposed in this paper. By using a simple example, we show how such a model can be used to forecast the drifts of the main characteristics of a CMOS circuit. Further, we demonstrate that this model can also be used to help the designer to choose and/or modify a circuit in order to minimize the hot-carrier induced degradations. Simulation results compared to the analytical study are also shown.
Citation:
Benoit Dubois, Jean-Baptiste Kammerer, Luc Hebrard, Francis Braun, "Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability," isqed, pp.53-58, 8th International Symposium on Quality Electronic Design (ISQED'07), 2007
Usage of this product signifies your acceptance of the Terms of Use.