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7th International Symposium on Quality Electronic Design (ISQED'06)
San Jose, California
March 27-March 29
ISBN: 0-7695-2523-7
Table of Contents
Introduction
pp. xviii-xix
ISQED Luncheon Speech
Session 5A.: IC-Package Design Challenges
Session 4C.: Technologies for Robust Design
Participating Organizations
Best Paper Award
ISQED Tutorials
Rajiv Joshi, IBM T J Watson Research Center, NY
Kaustav Banerjee, University of California, Santa Barbara, CA
Andre DeHon, California Institute of Technology, Pasadena, CA
pp. 4
Keith Bowman, Intel Corporation
Michael Orshansky, University of Texas-Austin
Sachin S. Sapatnekar, University of Minnesota
pp. 5
ISQED Panel Discussion
ISQED Plenary Session
Session 1A: Variation Aware Timing
Evelyn Grossar, IMEC,Kapeldreef , Leuven, Belgium
Michele Stucchi, IMEC,Kapeldreef , Leuven, Belgium
Karen Maex, IMEC,Kapeldreef , Leuven, Belgium
Wim Dehaene, K.U.Leuven, ESAT, Kasteelpark Arenberg 10,B-3001 Leuven, Belgium
pp. 25-30
Andrew B. Kahng, UC San Diego, La Jolla, CA
Bao Liu, UC San Diego, La Jolla, CA
Xu Xu, UC San Diego, La Jolla, CA
pp. 37-42
Zhuo Feng, Texas A&M University
Peng Li, Texas A&M University
Jiang Hu, Texas A&M University
pp. 43-50
Session 1B: High-Level Design Verification
Giuseppe Di Guglielmo, Universita di Verona ,Verona, Italy
Franco Fummi, Universita di Verona ,Verona, Italy
Cristina Marconcini, Universita di Verona ,Verona, Italy
Graziano Pravadelli, Universita di Verona ,Verona, Italy
pp. 57-62
Indradeep Ghosh, Fujitsu Laboratories of America, Sunnyvale, CA, USA
Mukul R. Prasad, Fujitsu Laboratories of America, Sunnyvale, CA, USA
pp. 63-70
C Karfa, Indian Institute of Technology, Kharagpur, India
C Mandal, Indian Institute of Technology, Kharagpur, India
D Sarkar, Indian Institute of Technology, Kharagpur, India
S R Pentakota, Indian Institute of Technology, Kharagpur, India
pp. 71-78
Session 1C.: Physical Planning
C. Yeh, Apache Design Sol.
G. Wilke, UFRGS, Brazil
H. Chen, Synopsys, CA, USA
S. Reddy, Fujitsu Laboratories of America, Inc., CA, USA
H. Nguyen, Fujitsu Laboratories of America, Inc., CA, USA
T. Miyoshi, Fujitsu Laboratories of America, Inc., CA, USA
W. Walker, Fujitsu Laboratories of America, Inc., CA, USA
R. Murgai, Fujitsu Laboratories of America, Inc., CA, USA
pp. 85-91
W.-L. Hung, Pennsylvania State University, University Park
G.M. Link, Pennsylvania State University, University Park
Yuan Xie, Pennsylvania State University, University Park
N. Vijaykrishnan, Pennsylvania State University, University Park
M. J. Irwin, Pennsylvania State University, University Park
pp. 98-104
Session 2A.: Robust Device and Circuit Design
Y. S. Chauhan, Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
C. Anghel, Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
F. Krummenacher, Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
R. Gillon, AMI Semiconductor, Belgium
A. Baguenier, 3Cadence Design Systems, France
pp. 109-114
Jin He, Peking University, Beijing, P.R.China
Xing Zhang, Peking University, Beijing, P.R.China
Ganggang Zhang, Peking University, Beijing, P.R.China
Mansun Chan, Hong Kong University of Science & Technology
Yangyuan Wang, Peking University, Beijing, China
pp. 115-120
Jin He, Peking University, Beijing, China
Xing Zhang, Peking University, Beijing, China
Ganggang Zhang, Peking University, Beijing, China
Yangyuan Wang, Peking University, Beijing, .China
pp. 127-132
Session 2B.: Power, Noise and Timing Issues in DSM Designs
Soheil Ghiasi, University of California, Davis
Po-Kuan Huang, University of California, Davis
pp. 141-146
Nahmsuk Oh, Synopsys Inc., 700 E. Middlefield Road, Mountain View, CA
Li Ding, Synopsys Inc., 700 E. Middlefield Road, Mountain View, CA
Alireza Kasnavi, Synopsys Inc., 700 E. Middlefield Road, Mountain View, CA
pp. 153-159
Emre Salman, University of Rochester
Eby G. Friedman, University of Rochester
Ali Dasdan, Synopsys, Inc., Mountain View, CA
Feroze Taraporevala, Synopsys, Inc., Mountain View, CA
Kayhan Kucukcakar, Synopsys, Inc., Mountain View, CA
pp. 159-164
Session 2C.: Memory Analysis
Fadi J. Kurdahi, University of California, Irvine
Ahmed M. Eltawil, University of California, Irvine
Young-Hwan Park, University of California, Irvine
Rouwaida N. Kanj, IBM Austin Research Labs
Sani R. Nassif, IBM Austin Research Labs
pp. 179-184
Young-Gu Kim, CAE Team, Semiconductor R&D Center
Sang-Hoon Lee, CAE Team, Semiconductor R&D Center
Dae-Han Kim, CAE Team, Semiconductor R&D Center
Dae-Han Kim, Flash Team, SRAM/Flash Product & Technology, Samsung
Jae-Woo Im, Flash Team, SRAM/Flash Product & Technology, Samsung
Sung-Eun Yu, CAE Team, Semiconductor R&D Center
Dae-Wook Kim, CAE Team, Semiconductor R&D Center
Young-Kwan Park, CAE Team, Semiconductor R&D Center
Jeong-Taek Kong, CAE Team, Semiconductor R&D Center
pp. 185-189
R. Venkatraman, LSI Logic Corporation, Milpitas, CA
R. Castagnetti, LSI Logic Corporation, Milpitas, CA
S. Ramesh, LSI Logic Corporation, Milpitas, CA
pp. 190-195
Makoto Sugihara, ISIT, 2-1-22 Momochihama, Sawara-ku, Fukuoka, Japan
Tohru Ishihara, Kyushu Univ., Fukuoka, Japan
Masanori Muroyama, Kyushu Univ., Fukuoka, Japan
Koji Hashimoto, Fukuoka Univ.,Fukuoka, Japan
pp. 196-203
Praveen Elakkumanan, University at Buffalo
Jente B Kuang, University at Buffalo IBM Austin Research Lab
Kevin Nowka, University at Buffalo IBM Austin Research Lab
Ramalingam Sridhar, University at Buffalo IBM Austin Research Lab
Rouwaida Kanj, University at Buffalo IBM Austin Research Lab
Sani Nassif, University at Buffalo IBM Austin Research Lab
pp. 204-209
Sanjay V. Kumar, University of Minnesota, Minneapolis
Chris H. Kim, University of Minnesota, Minneapolis
Sachin S. Sapatnekar, University of Minnesota, Minneapolis
pp. 210-218
Session 2D.: Posters
Krishna Raghuraman, Southern Illinois University, Carbondale, IL
Haibo Wang, Southern Illinois University, Carbondale, IL
Spyros Tragoudas, Southern Illinois University, Carbondale, IL
pp. 219-224
Kaiping Zeng, Darmstadt University of Technology, Germany
Sorin A. Huss, Darmstadt University of Technology, Germany
pp. 225-230
Yi-Le Huang, National Tsing-Hua University, China
Chun-Yao Wang, National Tsing-Hua University, China
Richard Yeh, SpringSoft, Inc., Taiwan
Shih-Chieh Chang, National Tsing-Hua University, China
Yung-Chih Chen, National Tsing-Hua University, China
pp. 231-236
Xinjie Wei, Tsinghua University, China
Yici Cai, Tsinghua University, China
Xianlong Hong, Tsinghua University, China
pp. 237-242
Qikai Chen, Purdue University, IN, USA
Mesut Meterelliyoz, Purdue University, IN, USA
Kaushik Roy, Purdue University, IN, USA
pp. 243-248
C. Tabery, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
M. Craig, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
G. Burbach, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
B. Wagner, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
S. McGowan, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
P. Etter, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
S. Roling, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
C. Haidinyak, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
E. Ehrichs, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
pp. 260-265
Xiongfei Meng, University of British Columbia, Canada
Resve Saleh, University of British Columbia, Canada
Karim Arabi, MC-Sierra, Inc., BC, Canada
pp. 266-271
Jeffrey Fan, University of California, Riverside
I-Fan Liao, University of California, Riverside
X.-D Sheldon, University of California, Riverside
Yici Cai, Tsinghua University, Beijing, China
Xianlong Hong, Tsinghua University, Beijing, China
pp. 272-277
K. Srinivasan, Georgia Institute of Technology
P. Muthana, Georgia Institute of Technology
R. Mandrekar, Georgia Institute of Technology
E. Engin, Georgia Institute of Technology
J. Choi, Georgia Institute of Technology
M. Swaminathan, Georgia Institute of Technology
pp. 284-291
Cheng Zhuo, Zhejiang University, Hangzhou, China
Jiang Hu, Texas A&M University, College Station, TX
Kangsheng Chen, Zhejiang University, Hangzhou, China
pp. 290-295
Arkan Abdulrahman, Southern Illinois University, Carbondale
Spyros Tragoudas, Southern Illinois University, Carbondale
pp. 300-305
Debjit Sinha, EECS, Northwestern University, Evanston, IL
Hai Zhou, EECS, Northwestern University, Evanston, IL
Narendra V. Shenoy, ATG, Synopsys Inc., Mountain View, CA
pp. 306-311
Zhiyu Liu, University of Wisconsin, Madison
Volkan Kursun, University of Wisconsin, Madison
pp. 318-323
Randy Bach, LSI Logic Inc., 1621 Barber Lane, Milpitas CA, USA
Bob Davis, LSI Logic Inc., 1621 Barber Lane, Milpitas CA, USA
Rich Laubhan, LSI Logic Inc., 1621 Barber Lane, Milpitas CA, USA
pp. 324-329
S. Baloch, Institute for System Level Integration, Alba Centre, Alba Campus, Livingston, EH54 7EG, UK
T. Arslan, University of Edinburgh, Kings Buildings, Edinburgh,EH9 3JL, UK
A. Stoica, Jet Propulsion Laboratory, NASA, 4800 Oak Grove Drive Pasadena, CA
pp. 330-345
Jean-Marc Philippe, CEA-List DRT/DTSI/SARC/LCEI, France
S?ebastien Pillement, University of Rennes (ENSSAT), Lannion, France
Olivier Sentieys, University of Rennes (ENSSAT), Lannion, France
pp. 334-339
Jia Wang, Northwestern University Evanston, IL
Hai Zhou, Northwestern University Evanston, IL
Ping-Chih Wu, Cadence Design Systems Inc., San Jose, CA
pp. 340-345
Zile Wei, University of California at Berkeley, CA
Donald Chai, University of California at Berkeley, CA
A. Richard Newton, University of California at Berkeley, CA
Andreas Kuehlmann, Cadence Berkeley Labs, Berkeley, CA, USA
pp. 346-351
Praveen Bhojwani, Texas A&M University, College Station, Texas
Rabi N. Mahapatra, Texas A&M University, College Station, Texas
pp. 358-363
Takeshi Matsumoto, Electronics Engineering, University of Tokyo
Hiroshi Saito, VLSI Design and Education Center, University of Tokyo
Masahiro Fujita, University of Aizu
pp. 370-375
C. Sanz, Universidad Complutense, 28040 Madrid, Spain
M. Prieto, Universidad Complutense, Madrid, Spain
A. Papanikolaou, IMEC v.z.w, Leuven, Belgium
M. Miranda, IMEC v.z.w, Leuven, Belgium
F. Catthoor, IMEC v.z.w, Leuven, Belgium
pp. 376-382
Biye Wang, San Jose State University
Lili He, San Jose State University
Morris Jones, San Jose State University
pp. 383-386
J. Balachandran, Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
S. Brebels, Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
G. Carchon, Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
W.De Raedt, Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
E. Beyne, Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
M. Kuijk, Vrije Universiteit Brussel,ETRO, Pleinlaan 2,1050 Brussel, Belgium
B. Nauwelaers, Katholieke Universiteit Leuven, ESAT, Kasteelpark Arenberg 10, 3001 Leuven, Belgium.
pp. 387-392
Yuichi Tanji, Kagawa University, Japan
Takayuki Watanabe, University of Shizuoka, Japan
Hidemasa Kubota, Shizuoka University, Japan
Hideki Asai, Shizuoka University, Japan
pp. 393-400
Session 3A.: Interconnect Analysis and Optimization
Rohit Singhal, Texas A & M University, College Station, TX
Gwan S. Choi, Texas A & M University, College Station, TX
Rabi Mahapatra, Texas A & M University, College Station, TX
pp. 407-412
Pu Liu, University of California, Riverside
Sheldon X.-D. Tan, University of California, Riverside
Bruce McGaughy, Cadence Design Systems Inc., San Jose, CA
Lifeng Wu, Cadence Design Systems Inc., San Jose, CA
pp. 413-418
Maged Ghoneima, Northwestern University
Yehea Ismail, Northwestern University
Muhammad Khellah, Circuit Research Lab, Intel Corporation
Vivek De, Circuit Research Lab, Intel Corporation
pp. 425-432
Session 3B: Digital Test and Diagnosis Techniques
E. Kalligeros, University of Ioannina, 45110 Ioannina, Greece
X. Kavousianos, University of Ioannina, 45110 Ioannina, Greece
D. Nikolos, Computer Engineering & Informatics Dept., University of Patras, 26500 Patras, Greece
pp. 433-438
Rajsekhar Adapa, Southern Illinois University Carbondale
Spyros Tragoudas, Southern Illinois University Carbondale
Maria K Michael, University of Cyprus
pp. 439-444
Li-Chung Hsu, SpringSoft, Inc., Hsinchu, Taiwan
Hung-Ming Chen, National Chiao Tung University, Hsinchu, Taiwan
pp. 451-456
E. Flanigan, Southern Illinois University at Carbondale
T. Haniotakis, Southern Illinois University at Carbondale
S. Tragoudas, Southern Illinois University at Carbondale
pp. 457-462
Vishal J. Mehta, UC, Santa Barbara,CA
Malgorzata Marek-Sadowska, UC, Santa Barbara,CA
Zhiyuan Wang, Cisco Systems Inc., San Jose, CA
Kun-Han Tsai, Mentor Graphics Corporation, Wilsonville, OR
Janusz Rajski, Mentor Graphics Corporation, Wilsonville, OR
pp. 463-472
Session 3C.: Back of Line DFM
Jeanne Bickford, IBM Microelectronics, Burlington, VT, USA
Jason Hibbeler, IBM Microelectronics, Burlington, VT, USA
Markus Buhler, IBM Deutschland Entwicklung GmbH, Boblingen, Germany
Jurgen Koehl, IBM Deutschland Entwicklung GmbH, Boblingen, Germany
Dirk Muller3, University of Bonn, Germany
Sven Peyer, University of Bonn, Germany
Christian Schulte, University of Bonn, Germany
pp. 473-478
Takumi Uezono, Tokyo Institute of Technology
Kenichi Okada, Tokyo Institute of Technology
Kazuya Masu, Tokyo Institute of Technology
pp. 479-484
Robert Aitken, ARM Physical IP, Inc., Sunnyvale, CA, USA
pp. 491-496
Arnaud Epinat, STMicroelectronics
N. Vijayaraghavan, STMicroelectronics
Matthieu Sautier, STMicroelectronics
Olivier Callen, STMicroelectronics
Sebastien Fabre, Philips Semiconductors
Ryan Ross, Freescale Semiconductor - Crolles2 Alliance Crolles, France
Paul Simon, Philips Semiconductors
Robin Wilson, STMicroelectronics
pp. 497-502
Hsin-Chyh Hsu, Institute of Electronics, National Chiao-Tung University, Taiwan
Ming-Dou Ker, Institute of Electronics, National Chiao-Tung University, Taiwan
pp. 503-506
ISQED Panel Discussion 2
ISQED Plenary Session 2
Session 4A.: Analog Test and Self-Checking Design
Qingqi Dou, University of Texas at Austin
Jacob A. Abraham, University of Texas at Austin
pp. 525-530
Amit Laknaur, Southern Illinois University, Carbondale, IL
Haibo Wang, Southern Illinois University, Carbondale, IL
pp. 531-536
J. L. Catalano, Universidad Tecnologica Nacional, Argentina
G. Peretti, Universidad Tecnologica Nacional, Argentina
E. Romero, Universidad Tecnologica Nacional, Argentina
C. Marques, Universidad Nacional de Cordoba, Medina Allende y Haya de Torre, Cordoba
pp. 543-550
Session 4B.: Power Aware Designs and Memory Management
Minh Q. Do, Chalmers University of Technology, Sweden
Mindaugas Dra?zd?ziulis, Chalmers University of Technology, Sweden
Per Larsson-Edefors, Chalmers University of Technology, Sweden
Lars Bengtsson, Chalmers University of Technology, Sweden
pp. 557-563
Saraju P. Mohanty, University of North Texas, Denton, TX
Ramakrishna Velagapudi, University of North Texas, Denton, TX
Elias Kougianos, University of North Texas, Denton, TX
pp. 564-569
Sri Hari Krishna Narayanan, Pennsylvania State University
Mahmut Kandemir, Pennsylvania State University
Ozcan Ozturk, Pennsylvania State University
pp. 570-575
Ozcan Ozturk, Pennsylvania State University
Mahmut Kandemir, Pennsylvania State University
Ibrahim Kolcu, University of Manchester, UK
pp. 576-584
Wei Zhao, Arizona State University, Tempe, AZ
Yu Cao, Arizona State University, Tempe, AZ
pp. 585-590
M. Thomas, MEMTEL, LLC.
J. Pathak, MEMTEL, LLC.
J. Payne, MEMTEL, LLC.
F. Leisenberger, Austriamicrosystems, AG
E. Wachmann, Austriamicrosystems, AG
G. Schatzberger, Austriamicrosystems, AG
A. Wiesner, Austriamicrosystems, AG
M. Schrems, Austriamicrosystems, AG
pp. 591-596
Tai-Xiang Lai, National Chiao-Tung University, Hsinchu, Taiw
Ming-Dou Ker, National Chiao-Tung University, Hsinchu, Taiw
pp. 597-602
Vivek Joshi, Indian Institute of Technology, Kanpur, India
Rajeev R. Rao, University of Michigan, Ann Arbor, MI
David Blaauw, University of Michigan, Ann Arbor, MI
Dennis Sylvester, University of Michigan, Ann Arbor, MI
pp. 611-616
G. M. Link, Pennsylvania State University
N. Vijaykrishnan, Pennsylvania State University
pp. 625-632
Kanak Agarwal, IBM Research, Austin, TX
Kevin Nowka, IBM Research, Austin, TX
Harmander Deogun, University of Michigan, Ann Arbor, MI
Dennis Sylvester, University of Michigan, Ann Arbor, MI
pp. 633-637
Session 5B.: IP, Interoperability: Design Optimization
Guangyu Sun, Tsinghua University, Beijing, China
Zhiqiang Gao, Tsinghua University, Beijing, China
Yi Xu, Tsinghua University, Beijing, China
pp. 671-675
Dimitris Kagaris, Southern Illinois University, Carbondale, IL
Themistoklis Haniotakis, Southern Illinois University, Carbondale, IL
pp. 682-690
Session 5C.: DSM Interconnect Challenges
Andrew B. Kahng, UCSD CSE and ECE Departments, La Jolla, CA
Kambiz Samadi, UCSD ECE Department, La Jolla, CA
Puneet Sharma, UCSD ECE Department, La Jolla, CA
pp. 691-696
Laureline David, STMicroelectronics, France
Stephane Martin, STMicroelectronics, France
Corinne Cregut, STMicroelectronics, France
Eric Balossier, STMicroelectronics, France
Frederic Nyer, STMicroelectronics, France
Fabrice Huret, LEST UMR CNRS 6165 , Brest, France
pp. 703-708
Changhao Yan, Tsinghua Univ., Beijing , China
Wenjian Yu, Tsinghua Univ., Beijing , China
Zeyi Wang, Tsinghua Univ., Beijing , China
pp. 709-716
Session 6A.: Leakage Analysis and Optimization
Sarvesh Bhardwaj, Electrical Engineering, Arizona State University, Tempe, AZ
Yu Cao, Electrical Engineering, Arizona State University, Tempe, AZ
Sarma Vrudhula, Computer Science and Engineering, Arizona State University, Tempe, AZ
pp. 717-722
Wang Yu, Tsinghua University, Beijing, China
Lin Hai, Tsinghua University, Beijing, China
Yang Huazhong, Tsinghua University, Beijing, China
Luo Rong, Tsinghua University, Beijing, China
Wang Hui, Tsinghua University, Beijing, China
pp. 723-728
Behnam Amelifard, University of Southern California
Massoud Pedram, University of Southern California
Farzan Fallah, Fujitsu Labs of America, Sunnyvale, CA
pp. 729-734
Akhilesh Kumar, University of Waterloo, ON, Canada
Mohab Anis, University of Waterloo, ON, Canada
pp. 735-740
Session 6B.: System Level Designs and Reliability Models
Bhaskar J. Karmakar, DSP Systems, Texas Instruments, Bangalore, India.
V. Kalyana Chakravarty, DSP Systems, Texas Instruments, Bangalore, India.
R. Venkatraman, DSP Systems, Texas Instruments, Bangalore, India.
Jagdish C. Rao, DSP Systems, Texas Instruments, Bangalore, India.
pp. 769-774
I.-C. Lin, Pennsylvania State University
S. Srinivasan, Pennsylvania State University
N. Vijaykrishnan, Pennsylvania State University
N. Dhanwada, IBM Electronic Design Automation Systems and Technology Group
pp. 775-780
Session 6C.: Modeling for DFM
Usha Narasimha, Texas Instruments Inc., Dallas, TX
Binu Abraham, Texas Instruments Inc., Dallas, TX
Nagaraj NS, Texas Instruments Inc., Dallas, TX
pp. 795-800
S. Tirumala, Synopsys Inc, California, USA
Y. Mahotin, Synopsys Inc, California, USA
X. Lin, Synopsys Inc, California, USA
V. Moroz, Synopsys Inc, California, USA
L. Smith, Synopsys Inc, California, USA
S. Krishnamurthy, Synopsys Inc, California, USA
L. Bomholt, Synopsys Inc, California, USA
D. Pramanik, Synopsys Inc, California, USA
pp. 801-806
Victor Moroz, Synopsys, Inc., Mountain View, CA
Lee Smith, Synopsys, Inc., Mountain View, CA
Xi-Wei Lin, Synopsys, Inc., Mountain View, CA
Dipu Pramanik, Synopsys, Inc., Mountain View, CA
Greg Rollins, Synopsys, Inc., Mountain View, CA
pp. 807-812
Author Index
ISQED 2007 Call for Papers
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