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- ISQED
- 2006
- 7th International Symposium on Quality Electronic Design (ISQED'06)
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7th International Symposium on Quality Electronic Design (ISQED'06) San Jose, California March 27-March 29 ISBN: 0-7695-2523-7 Table of Contents
 | Introduction |
 | ISQED Tutorials |
Andre DeHon, California Institute of Technology, Pasadena, CA pp. 4
 | ISQED Panel Discussion |
 | ISQED Plenary Session |
 | Session 1A: Variation Aware Timing |
Wim Dehaene, K.U.Leuven, ESAT, Kasteelpark Arenberg 10,B-3001 Leuven, Belgium pp. 25-30
Bao Liu, UC San Diego, La Jolla, CA
Xu Xu, UC San Diego, La Jolla, CA pp. 37-42
 | Session 1B: High-Level Design Verification |
C Karfa, Indian Institute of Technology, Kharagpur, India
C Mandal, Indian Institute of Technology, Kharagpur, India
D Sarkar, Indian Institute of Technology, Kharagpur, India pp. 71-78
 | Session 1C.: Physical Planning |
S. Reddy, Fujitsu Laboratories of America, Inc., CA, USA
H. Nguyen, Fujitsu Laboratories of America, Inc., CA, USA
T. Miyoshi, Fujitsu Laboratories of America, Inc., CA, USA
W. Walker, Fujitsu Laboratories of America, Inc., CA, USA
R. Murgai, Fujitsu Laboratories of America, Inc., CA, USA pp. 85-91
W.-L. Hung, Pennsylvania State University, University Park
G.M. Link, Pennsylvania State University, University Park
Yuan Xie, Pennsylvania State University, University Park
M. J. Irwin, Pennsylvania State University, University Park pp. 98-104
 | ISQED Luncheon Speech |
 | Session 2A.: Robust Device and Circuit Design |
Y. S. Chauhan, Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
C. Anghel, Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland
F. Krummenacher, Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland pp. 109-114
Jin He, Peking University, Beijing, P.R.China
Mansun Chan, Hong Kong University of Science & Technology pp. 115-120
Jin He, Peking University, Beijing, China pp. 127-132
Sujit Dey, University of California at San Diego pp. 133-140
 | Session 2B.: Power, Noise and Timing Issues in DSM Designs |
Li Ding, Synopsys, Mountain View, CA pp. 147-152
Nahmsuk Oh, Synopsys Inc., 700 E. Middlefield Road, Mountain View, CA
Li Ding, Synopsys Inc., 700 E. Middlefield Road, Mountain View, CA pp. 153-159
 | Session 2C.: Memory Analysis |
Dae-Han Kim, Flash Team, SRAM/Flash Product & Technology, Samsung
Jae-Woo Im, Flash Team, SRAM/Flash Product & Technology, Samsung pp. 185-189
S. Ramesh, LSI Logic Corporation, Milpitas, CA pp. 190-195
Kevin Nowka, University at Buffalo IBM Austin Research Lab
Sani Nassif, University at Buffalo IBM Austin Research Lab pp. 204-209
 | Session 2D.: Posters |
Haibo Wang, Southern Illinois University, Carbondale, IL pp. 219-224
Peng Li, Texas A&M University, College Station, TX pp. 254-259
C. Tabery, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
M. Craig, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
G. Burbach, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
B. Wagner, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
S. McGowan, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
P. Etter, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
S. Roling, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
C. Haidinyak, Advanced Micro Devices, One AMD Place, Sunnyvale, CA
E. Ehrichs, Advanced Micro Devices, One AMD Place, Sunnyvale, CA pp. 260-265
Yici Cai, Tsinghua University, Beijing, China pp. 272-277
E. Engin, Georgia Institute of Technology
J. Choi, Georgia Institute of Technology pp. 284-291
Jiang Hu, Texas A&M University, College Station, TX pp. 290-295
Hai Zhou, EECS, Northwestern University, Evanston, IL pp. 306-311
Randy Bach, LSI Logic Inc., 1621 Barber Lane, Milpitas CA, USA
Bob Davis, LSI Logic Inc., 1621 Barber Lane, Milpitas CA, USA
Rich Laubhan, LSI Logic Inc., 1621 Barber Lane, Milpitas CA, USA pp. 324-329
S. Baloch, Institute for System Level Integration, Alba Centre, Alba Campus, Livingston, EH54 7EG, UK
T. Arslan, University of Edinburgh, Kings Buildings, Edinburgh,EH9 3JL, UK
A. Stoica, Jet Propulsion Laboratory, NASA, 4800 Oak Grove Drive Pasadena, CA pp. 330-345
Jia Wang, Northwestern University Evanston, IL
Hai Zhou, Northwestern University Evanston, IL pp. 340-345
Zile Wei, University of California at Berkeley, CA pp. 346-351
Hiroshi Saito, VLSI Design and Education Center, University of Tokyo pp. 370-375
C. Sanz, Universidad Complutense, 28040 Madrid, Spain
M. Prieto, Universidad Complutense, Madrid, Spain pp. 376-382
J. Balachandran, Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
S. Brebels, Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
G. Carchon, Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
W.De Raedt, Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
E. Beyne, Microwave and RF Systems Group, IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium
M. Kuijk, Vrije Universiteit Brussel,ETRO, Pleinlaan 2,1050 Brussel, Belgium
B. Nauwelaers, Katholieke Universiteit Leuven, ESAT, Kasteelpark Arenberg 10, 3001 Leuven, Belgium. pp. 387-392
 | Session 3A.: Interconnect Analysis and Optimization |
Yu Cao, Arizona State University pp. 401-406
Pu Liu, University of California, Riverside
Lifeng Wu, Cadence Design Systems Inc., San Jose, CA pp. 413-418
Taeyong Je, Hanynag Univ., Ansan, Kyunggi-do, Korea pp. 419-424
Vivek De, Circuit Research Lab, Intel Corporation pp. 425-432
 | Session 3B: Digital Test and Diagnosis Techniques |
D. Nikolos, Computer Engineering & Informatics Dept., University of Patras, 26500 Patras, Greece pp. 433-438
E. Flanigan, Southern Illinois University at Carbondale pp. 457-462
 | Session 3C.: Back of Line DFM |
Markus Buhler, IBM Deutschland Entwicklung GmbH, Boblingen, Germany
Jurgen Koehl, IBM Deutschland Entwicklung GmbH, Boblingen, Germany pp. 473-478
Ryan Ross, Freescale Semiconductor - Crolles2 Alliance Crolles, France pp. 497-502
Hsin-Chyh Hsu, Institute of Electronics, National Chiao-Tung University, Taiwan
Ming-Dou Ker, Institute of Electronics, National Chiao-Tung University, Taiwan pp. 503-506
 | ISQED Panel Discussion 2 |
 | ISQED Plenary Session 2 |
 | Session 4A.: Analog Test and Self-Checking Design |
Haibo Wang, Southern Illinois University, Carbondale, IL pp. 531-536
G. Peretti, Universidad Tecnologica Nacional, Argentina
E. Romero, Universidad Tecnologica Nacional, Argentina
C. Marques, Universidad Nacional de Cordoba, Medina Allende y Haya de Torre, Cordoba pp. 543-550
 | Session 4B.: Power Aware Designs and Memory Management |
Minh Q. Do, Chalmers University of Technology, Sweden pp. 557-563
 | Session 4C.: Technologies for Robust Design |
Wei Zhao, Arizona State University, Tempe, AZ
Yu Cao, Arizona State University, Tempe, AZ pp. 585-590
Vivek Joshi, Indian Institute of Technology, Kanpur, India pp. 611-616
 | Session 5A.: IC-Package Design Challenges |
 | Session 5B.: IP, Interoperability: Design Optimization |
Yi Xu, Tsinghua University, Beijing, China pp. 671-675
 | Session 5C.: DSM Interconnect Challenges |
 | Session 6A.: Leakage Analysis and Optimization |
Yu Cao, Electrical Engineering, Arizona State University, Tempe, AZ
Sarma Vrudhula, Computer Science and Engineering, Arizona State University, Tempe, AZ pp. 717-722
Wang Yu, Tsinghua University, Beijing, China
Lin Hai, Tsinghua University, Beijing, China
Luo Rong, Tsinghua University, Beijing, China
Wang Hui, Tsinghua University, Beijing, China pp. 723-728
 | Session 6B.: System Level Designs and Reliability Models |
N. Dhanwada, IBM Electronic Design Automation Systems and Technology Group pp. 775-780
 | Session 6C.: Modeling for DFM |
X. Lin, Synopsys Inc, California, USA pp. 801-806
 | Author Index |
 | Participating Organizations |
 | Best Paper Award |
 | ISQED 2007 Call for Papers | Usage of this product signifies your acceptance of the Terms of Use.
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