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7th International Symposium on Quality Electronic Design (ISQED'06)
The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability
San Jose, California
March 27-March 29
ISBN: 0-7695-2523-7
| ASCII Text | x | ||
| R. Venkatraman, R. Castagnetti, S. Ramesh, "The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability," Quality Electronic Design, International Symposium on, pp. 190-195, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006. | |||
| BibTex | x | ||
| @article{ 10.1109/ISQED.2006.134, author = {R. Venkatraman and R. Castagnetti and S. Ramesh}, title = {The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2523-7}, pages = {190-195}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.134}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Quality Electronic Design, International Symposium on TI - The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability SN - 0-7695-2523-7 SP190 EP195 A1 - R. Venkatraman, A1 - R. Castagnetti, A1 - S. Ramesh, PY - 2006 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER - | |||
It has been recognized that as CMOS technology scales, the accompanied scaling of the conventional 6T-SRAM bitcell will require careful assessment of the role of device variations on its stability, electrical performance and leakage. As part of our SRAM design methodology, we have studied the statistics of local and across-wafer variations in bitcell-related parameters by using a series of specialized electrical test structures. The resulting quantification of the device variations are useful towards developing accurate mismatch models that can in turn be used to design not only robust SRAM bitcells but also functionally robust memory arrays wherein the role of bitline leakage and the statistics of ?tail-bits? are
Citation:
R. Venkatraman, R. Castagnetti, S. Ramesh, "The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability," isqed, pp.190-195, 7th International Symposium on Quality Electronic Design (ISQED'06), 2006
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