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Sixth International Symposium on Quality of Electronic Design (ISQED'05)
San Jose, California
March 21-March 23
ISBN: 0-7695-2301-3
Table of Contents
Session 7B: Issues in On-Chip Communication and Analog/RF Designs
null
Session 7C: Robust Design under Parameter Variations
Tutorial I
Tutorial II
Session EP1
Plenary Session 1P
Session 1A: Tools and Flows for Quality Design
Alex Gyure, Synopsys, Inc., Mountain View, CA
Alireza Kasnavi, Synopsys, Inc., Mountain View, CA
Sam Lo, Synopsys, Inc., Mountain View, CA
Peivand F. Tehrani, Synopsys, Inc., Mountain View, CA
William Shu, Synopsys, Inc., Mountain View, CA
Mahmoud Shahram, Synopsys, Inc., Mountain View, CA
Joddy W. Wang, Synopsys, Inc., Mountain View, CA
Jindrich Zedja, Synopsys, Inc., Mountain View, CA
pp. 28-34
Luo Chun, Southeast University, P.R. China
Yang Jun, Southeast University, P.R. China
Shi Longxing, Southeast University, P.R. China
Wu XuFan, Southeast University, P.R. China
Zhang Yu, Southeast University, P.R. China
pp. 40-45
Session 1B: High Level Power/Noise Reduction Techniques
Dongku Kang, Purdue University, West Lafayette, IN
Yiran Chen, Purdue University, West Lafayette, IN
Kaushik Roy, Purdue University, West Lafayette, IN
pp. 48-53
Shivakumar Swaminathan, IBM Microelectronics, Research Triangle Park, NC
Sanjay B. Patel, Qualcomm, Research Triangle Park, NC
James Dieffenderfer, Qualcomm, Research Triangle Park, NC
Joel Silberman, IBM Research, Yorktown Heights, NY
pp. 54-58
Kee-Jong Kim, Purdue University, West Lafayette, IN; LG-Philips LCD, Korea
Chris H. Kim, University of Minnesota, Minneapolis, MN
Kaushik Roy, Purdue University, West Lafayette, IN
pp. 59-64
David Roberts, University of Michigan, USA
Todd Austin, University of Michigan, USA
David Blauww, University of Michigan, USA
Trevor Mudge, University of Michigan, USA
Kriszti?n Flautner, ARM Ltd., UK
pp. 65-70
Session 1C: Leakage and Dynamic Power Issues
Bhavana Jharia, Indian Institute of Technology, India
S. Sarkar, Indian Institute of Technology, India
R. P. Agarwal, Indian Institute of Technology, India
pp. 72-76
Jayakumaran Sivagnaname, The University of Michigan, Ann Arbor, MI
Hung C. Ngo, IBM Austin Research Laboratory, Austin, TX
Kevin J. Nowka, IBM Austin Research Laboratory, Austin, TX
Robert K. Montoye, IBM Austin Research Laboratory, Austin, TX
Richard B. Brown, The University of Michigan, Ann Arbor, MI
pp. 83-87
Harmander Singh Deogun, University of Michigan, Ann Arbor, MI
Rahul Rao, University of Michigan, Ann Arbor, MI
Dennis Sylvester, University of Michigan, Ann Arbor, MI
Richard Brown, University of Utah, Salt Lake City, UT
Kevin Nowka, Austin Research Laboratories, IBM, Austin, TX
pp. 88-93
Session 1D: Poster Session
Jin He, University of California, Berkeley, CA
Jane Xi, University of California, Berkeley, CA
Mansun Chan, University of California, Berkeley, CA
Hui Wan, University of California, Berkeley, CA
Mohan Dunga, University of California, Berkeley, CA
Babak Heydari, University of California, Berkeley, CA
Ali M. Niknejad, University of California, Berkeley, CA
Chenming Hu, University of California, Berkeley, CA
pp. 96-101
Carlo Roma, STMicroelectronics, Agrate Brianza, Milan, Italy
Pierluigi Daglio, STMicroelectronics, Agrate Brianza, Milan, Italy
Guido De Sandre, STMicroelectronics, Agrate Brianza, Milan, Italy
Marco Pasotti, STMicroelectronics, Agrate Brianza, Milan, Italy
Marco Poles, STMicroelectronics, Agrate Brianza, Milan, Italy
pp. 107-112
Mini Nanua, Sun MicroSystems
David Blaauw, University of Michigan
Chanhee Oh, Nascentric Inc.
pp. 113-117
Arun Shrimali, Texas Instruments India
Anand Venkitachalam, Texas Instruments India
Ravi Arora, Texas Instruments India
pp. 123-127
C. K. Tang, University of Arkansas, Fayetteville, AR
P. K. Lala, University of Arkansas, Fayetteville, AR
J. P. Parkerson, University of Arkansas, Fayetteville, AR
pp. 128-132
C. Talarico, University of Arizona, Tucson, AZ
B. Pillilli, University of Arizona, Tucson, AZ
K. L. Vakati, University of Arizona, Tucson, AZ
J. M. Wang, University of Arizona, Tucson, AZ
pp. 133-136
Zhaojun Wo, University of Massachusetts, Amherst, MA
Israel Koren, University of Massachusetts, Amherst, MA
pp. 137-142
DiaaEldin Khalil, Ain Shams University, Cairo, Egypt
Mohamed Dessouky, Ain Shams University, Cairo, Egypt
Vincent Bourguet, University of Paris 6, Paris, France
Marie-Minerve Louerat, University of Paris 6, Paris, France
Andreia Cathelin, STMicroelectronics - Central R&D/DAIS, Crolles, France
Hani Ragai, Ain Shams University, Cairo, Egypt
pp. 143-147
Atsushi Kurokawa, Semiconductor Technology Academic Research Center (STARC); Waseda University
Masaharu Yamamoto, Semiconductor Technology Academic Research Center (STARC)
Nobuto Ono, Jedat Innovation Inc.
Tetsuro Kage, Tokyo National College of Technology
Yasuaki Inoue, Waseda University
Hiroo Masuda, Semiconductor Technology Academic Research Center (STARC)
pp. 153-158
Haixia Gao, Microelectronics Institute, Xidian University, China
Yintang Yang, Microelectronics Institute, Xidian University, China
Xiaohua Ma, Microelectronics Institute, Xidian University, China
Gang Dong, Microelectronics Institute, Xidian University, China
pp. 159-163
Yong-Chan Ban, Samsung Electronics Co., Ltd, Korea
Soo-Han Choi, Samsung Electronics Co., Ltd, Korea
Ki-Hung Lee, Samsung Electronics Co., Ltd, Korea
Dong-Hyun Kim, Samsung Electronics Co., Ltd, Korea
Ji-Suk Hong, Samsung Electronics Co., Ltd, Korea
Yoo-Hyon Kim, Samsung Electronics Co., Ltd, Korea
Moon-Hyun Yoo, Samsung Electronics Co., Ltd, Korea
Jeong-Taek Kong, Samsung Electronics Co., Ltd, Korea
pp. 169-174
Harmander Singh Deogun, University of Michigan, Ann Arbor, MI
Dennis Sylvester, University of Michigan, Ann Arbor, MI
David Blaauw, University of Michigan, Ann Arbor, MI
pp. 175-180
Hua Xiang, IBM T.J. Watson Research Center, Yorktown Heights, NY
Kai-Yuan Chao, Intel Corporation, Hillsboro, Oregon
Martin D. F. Wong, UIUC, Urbana, IL
pp. 181-186
J. Huynh, San Jose State University, CA
B. Ngo, San Jose State University, CA
M. Pham, San Jose State University, CA
L. He, San Jose State University, CA
pp. 187-192
R. Castagnetti, LSI Logic Corporation, Milpitas, CA
R. Venkatraman, LSI Logic Corporation, Milpitas, CA
B. Bartz, LSI Logic Corporation, Milpitas, CA
C. Monzel, LSI Logic Corporation, Milpitas, CA
T. Briscoe, LSI Logic Corporation, Milpitas, CA
A. Teene, LSI Logic Corporation, Milpitas, CA
S. Ramesh, LSI Logic Corporation, Milpitas, CA
pp. 193-196
Khadija Stewart, Southern Illinois University Carbondale
Themistoklis Haniotakis, Southern Illinois University Carbondale
Spyros Tragoudas, Southern Illinois University Carbondale
pp. 197-201
M. Welling, Southern Illinois University at Carbondale
S. Tragoudas, Southern Illinois University at Carbondale
H. Wang, Southern Illinois University at Carbondale
pp. 202-207
Young-Seok Hong, Samsung Electronics Co., Ltd., Korea
Heeseok Lee, Samsung Electronics Co., Ltd., Korea
Joon-Ho Choi, Samsung Electronics Co., Ltd., Korea
Moon-Hyun Yoo, Samsung Electronics Co., Ltd., Korea
Jeong-Taek Kong, Samsung Electronics Co., Ltd., Korea
pp. 208-212
Yuchun Ma, Tsinghua University, Beijing, China
Xianlong Hong, Tsinghua University, Beijing, China
Sheqin Dong, Tsinghua University, Beijing, China
Song Chen, Tsinghua University, Beijing, China
Chung-Kuan Cheng, University of California, San Diego
pp. 213-219
ISQED Luncheon Speech
Session 2A: Test Application and Cost Reduction
E. Kalligeros, University of Patras, Greece; Research Academic Computer Technology Institute, Greece
D. Kaseridis, University of Patras, Greece; Research Academic Computer Technology Institute, Greece
X. Kavousianos, University of Ioannina, Greece
D. Nikolos, University of Patras, Greece; Research Academic Computer Technology Institute, Greece
pp. 226-231
Th. Haniotakis, Southern Illinois University Carbondale
S. Tragoudas, Southern Illinois University Carbondale
G. Pani, Southern Illinois University Carbondale
pp. 232-237
Yinhe Han, Chinese Academy of Sciences, Beijing; Graduate School of Chinese Academy of Sciences, Beijing
Yu Hu, Chinese Academy of Sciences, Beijing
Huawei Li, Chinese Academy of Sciences, Beijing; Graduate School of Chinese Academy of Sciences, Beijing
Xiaowei Li, Chinese Academy of Sciences, Beijing; Graduate School of Chinese Academy of Sciences, Beijing
pp. 238-243
BIST-Guided ATPG (Abstract)
Ahmad A. Al-Yamani, Stanford University, Stanford, CA; LSI Logic Corporation, Milpitas, CA
Edward J. McCluskey, Stanford University, Stanford, CA
pp. 244-249
Irith Pomeranz, Purdue University, W. Lafayette, IN
Sudhakar M. Reddy, University of Iowa, Iowa City, IA
pp. 250-255
Session 2B: DFM and Physical Layout
Xin Wang, Synopsys Inc., Mountain View, CA
Charles C. Chiang, Synopsys Inc., Mountain View, CA
Jamil Kawa, Synopsys Inc., Mountain View, CA
Qing Su, Synopsys Inc., Mountain View, CA
pp. 258-263
Puneet Gupta, University of California at San Diego
Andrew B. Kahng, University of California at San Diego
Dennis Sylvester, University of Michigan at Ann Arbor
Jie Yang, University of Michigan at Ann Arbor
pp. 270-275
Jay Jahangiri, Mentor Graphics Corporation
David Abercrombie, Mentor Graphics Corporation
pp. 276-282
Session 2C: Performance and Reliability Analysis for Yield Optimization
Rahul Rao, University of Michigan, Ann Arbor, MI
Kanak Agarwal, University of Michigan, Ann Arbor, MI
Anirudh Devgan, Austin Research Laboratories, IBM, Austin, TX
Kevin Nowka, Austin Research Laboratories, IBM, Austin, TX
Dennis Sylvester, University of Michigan, Ann Arbor, MI
Richard Brown, University of Utah, Salt Lake City, UT
pp. 284-290
Dipanjan Sengupta, University of British Columbia, Canada
Resve Saleh, University of British Columbia, Canada
pp. 291-296
Syed M. Alam, Freescale Semiconductor
Frank L. Wei, Massachusetts Institute of Technology
Chee Lip Gan, Nanyang Technological University
Carl V. Thompson, Massachusetts Institute of Technology
Donald E. Troxel, Massachusetts Institute of Technology
pp. 303-308
Session 3A: Functional Verification and Test Generation
Anat Dahan, IBM Haifa Research Lab, Haifa Israel
Daniel Geist, IBM Haifa Research Lab, Haifa Israel
Leonid Gluhovsky, IBM Haifa Research Lab, Haifa Israel
Dmitry Pidan, IBM Haifa Research Lab, Haifa Israel
Gil Shapir, IBM Haifa Research Lab, Haifa Israel
Yaron Wolfsthal, IBM Haifa Research Lab, Haifa Israel
Lyes Benalycherif, ST Microelectronics, Grenoble, France
Romain Kamdem, ST Microelectronics, Grenoble, France
Younes Lahbib, ST Microelectronics, Grenoble, France
pp. 310-315
Nicola Bombieri, Universit? di Verona, Italy
Franco Fummi, Universit? di Verona, Italy
Graziano Pravadelli, Universit? di Verona, Italy
pp. 321-326
Maria K. Michael, University of Cyprus
Stelios Neophytou, University of Cyprus
Spyros Tragoudas, Southern Illinois University
pp. 327-332
Session 3B: Power Delivery and Distribution
Navin Srivastava, University of California, Santa Barbara, CA
Xiaoning Qi, Sun Microsystems Inc., Sunnyvale, CA
Kaustav Banerjee, University of California, Santa Barbara, CA
pp. 346-351
Session 3C: Quality System Level Design and Synthesis
S. Tosun, Syracuse University
O. Ozturk, Pennsylvania State University
N. Mansouri, Syracuse University
E. Arvas, Syracuse University
M. Kandemir, Pennsylvania State University
Y. Xie, Pennsylvania State University
W-L. Hung, Pennsylvania State University
pp. 364-369
Haixia Gao, Xidian University, China
Yintang Yang, Xidian University, China
Xiaohua Ma, Xidian University, China
Gang Dong, Xidian University, China
pp. 370-374
S. Tosun, Syracuse University
N. Mansouri, Syracuse University
E. Arvas, Syracuse University
M. Kandemir, Pennsylvania State University
Y. Xie, Pennsylvania State University
W-L. Hung, Pennsylvania State University
pp. 375-380
Session 4A: DFM for Circuit Design
Xiaojun Li, University of Maryland, College Park
B. Huang, University of Maryland, College Park
J. Qin, University of Maryland, College Park
X. Zhang, University of Maryland, College Park
M. Talmor, University of Maryland, College Park
Z. Gur, University of Maryland, College Park
Joseph B. Bernstein, University of Maryland, College Park
pp. 382-389
Henry H. Y. Chan, Microelectronics and Computer Systems Laboratory, Canada
Zeljko Zilic, Microelectronics and Computer Systems Laboratory, Canada
pp. 390-395
Kambiz Rahimi, University of Washington, Seattle
Chris Diorio, University of Washington, Seattle
pp. 396-401
Session 4B: Leakage and Reliability Management
Saibal Mukhopadhyay, Purdue University, West Lafayette, IN
Keunwoo Kim, IBM T. J. Watson Research Center, Yorktown Heights, NY
Jae-Joon Kim, IBM T. J. Watson Research Center, Yorktown Heights, NY
Shih-Hsien Lo, IBM T. J. Watson Research Center, Yorktown Heights, NY
Rajiv V. Joshi, IBM T. J. Watson Research Center, Yorktown Heights, NY
Ching-Te Chuang, IBM T. J. Watson Research Center, Yorktown Heights, NY
Kaushik Roy, Purdue University, West Lafayette, IN
pp. 410-415
Ananth Somayaji Goda, Texas Instruments India Pvt Ltd, Bangalore, India
Gautam Kapila, Texas Instruments India Pvt Ltd, Bangalore, India
pp. 416-420
Puneet Gupta, Blaze DFM, Inc., Sunnyvale, CA
Andrew B. Kahng, Blaze DFM, Inc., Sunnyvale, CA; UCSD, La Jolla, CA
Puneet Sharma, UCSD, La Jolla, CA
pp. 421-426
O. Semenov, University of Waterloo, Canada
H. Sarbishaei, University of Waterloo, Canada
M. Sachdev, University of Waterloo, Canada
pp. 427-432
Session 4C: Analog Test and BIST
Amit Laknaur, Southern Illinois University Carbondale, Carbondale, IL
Haibo Wang, Southern Illinois University Carbondale, Carbondale, IL
pp. 434-439
L. Dermentzoglou, University of Athens, Greece
Y. Tsiatouhas, University of Ioannina, Greece
A. Arapoyanni, University of Athens, Greece
pp. 448-452
Swarup Bhunia, Purdue University, West Lafayette, IN
Hamid Mahmoodi, Purdue University, West Lafayette, IN
Debjyoti Ghosh, Purdue University, West Lafayette, IN
Kaushik Roy, Purdue University, West Lafayette, IN
pp. 453-458
Session EP2
Plenary Session 2P
Aki Fujimura, Cadence Design Systems, Inc.
pp. 463-463
Session 5A: Design Methods and Tools in DSM
Jihyun Lee, Northeastern University, Boston, MA
Yong-Bin Kim, Northeastern University, Boston, MA
pp. 470-475
Yuanzhong (Paul) Zhou, Fairchild Semiconductor, South Portland, ME
Duane Connerney, Fairchild Semiconductor, South Portland, ME
Ronald Carroll, Fairchild Semiconductor, South Portland, ME
Timwah Luk, Fairchild Semiconductor, South Portland, ME
pp. 476-481
Subhrajit Bhattacharya, IBM T.J. Watson Research Center, Yorktown Heights, NY
John Darringer, IBM T.J. Watson Research Center, Yorktown Heights, NY
Daniel Ostapko, IBM T.J. Watson Research Center, Yorktown Heights, NY
Youngsoo Shin, Korea Advanced Institute of Science and Technology, Republic of Korea
pp. 482-487
Session 5B: Design Techniques for Leakage Reduction
Saibal Mukhopadhyay, Purdue University, West Lafayette, IN
Hamid Mahmoodi, Purdue University, West Lafayette, IN
Kaushik Roy, Purdue University, West Lafayette, IN
pp. 490-495
Xiaojun Li, University of Maryland, College Park, MD
Joerg D. Walter, University of Maryland, College Park, MD
Joseph B. Bernstein, University of Maryland, College Park, MD
pp. 496-502
Session 5C: Variability Issues in Nanoscale Circuits
Norman Gunther, Santa Clara University, CA
Emad Hamadeh, Santa Clara University, CA; Applied Micro C. Co. (AMCC), Sunnyvale, CA
Darrell Niemann, Santa Clara University, CA
Iliya Pesic, Santa Clara University, CA; Silvaco International, Santa Clara, CA
Mahmud Rahman, Santa Clara University, CA
pp. 510-515
Paul Friedberg, University of California, Berkeley, CA
Yu Cao, University of California, Berkeley, CA
Jason Cain, University of California, Berkeley, CA
Ruth Wang, University of California, Berkeley, CA
Jan Rabaey, University of California, Berkeley, CA
Costas Spanos, University of California, Berkeley, CA
pp. 516-521
Session 6A: Issues in Noise and Timing
Shahin Nazarian, University of Southern California, Los Angeles, CA
Massoud Pedram, University of Southern California, Los Angeles, CA
Emre Tuncer, Magma Design Automation, Santa Clara, CA
Tao Lin, Magma Design Automation, Santa Clara, CA
pp. 536-541
Zhenyu Qi, University of California, Riverside
Hang Li, University of California, Riverside
Sheldon X.-D. Tan, University of California, Riverside
Lifeng Wu, Cadence Design Systems Inc. San Jose, CA
Yici Cai, Tsinghua University, Beijing, China
Xianlong Hong, Tsinghua University, Beijing, China
pp. 542-547
Session 6B: Design Approaches for System in Package (SiP)
Anru Wang, University of California, Santa Cruz
Wayne Dai, University of California, Santa Cruz
pp. 562-566
Chung-Seok(Andy) Seo, Georgia Institute of Technology, Atlanta, GA
Abhijit Chatterjee, Georgia Institute of Technology, Atlanta, GA
Nan M. Jokerst, Duke University, Durham, NC
pp. 567-572
Meigen Shen, Royal Institute of Technology (KTH), Sweden
Li-Rong Zheng, Royal Institute of Technology (KTH), Sweden
Esa Tjukanoff, University of Turku, Finland
Jouni Isoaho, University of Turku, Finland
Hannu Tenhunen, Royal Institute of Technology (KTH), Sweden
pp. 573-578
Session 6C: DSM Interconnect Issues
Muzhou Shao, Synopsys Inc., Mountain View, CA
Youxin Gao, Synopsys Inc., Mountain View, CA
Li-Pen Yuan, Synopsys Inc., Mountain View, CA
Hung-Ming Chen, National Chiao Tung University, Hsinchu, Taiwan
Martin DF Wong, University of Illinois at Urbana-Champaign, Urbana, IL
pp. 580-585
Atsushi Kurokawa, STARC; Waseda University
Toshiki Kanamoto, Renesas Technology Corp.
Tetsuya Ibe, Sanyo Electric Corp.
Akira Kasebe, Meitec Corp.
Chang Wei Fong, Cristal Cosmotech Corp.
Tetsuro Kage, Tokyo National College of Technology
Yasuaki Inoue, Waseda University
Hiroo Masuda, STARC
pp. 586-591
Jiaxing Sun, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China
Yun Zheng, CEC Huada Electronic Design Co., Ltd., Beijing, China
Qing Ye, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China
Tianchun Ye, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China
pp. 598-602
Pu Liu, University of California, Riverside, CA
Zhenyu Qi, University of California, Riverside, CA
Sheldon X.-D. Tan, University of California, Riverside, CA
pp. 603-608
Session 7A: Advances in Floor Planning
Jingyu Xu, Tsinghua Univ., Beijing, China
Xianlong Hong, Tsinghua Univ., Beijing, China
Tong Jing, Tsinghua Univ., Beijing, China
Yang Yang, Tsinghua Univ., Beijing, China
pp. 616-621
Hua Xiang, IBM T.J. Watson Research Center, Yorktown Heights, NY
I-Min Liu, Cadence Design System, San Jose, CA
Martin D. F. Wong, UIUC, Urbana, IL
pp. 622-627
Song Chen, Tsinghua Univ. China
Xianlong Hong, Tsinghua Univ. China
Sheqin Dong, Tsinghua Univ. China
Yuchun Ma, Tsinghua Univ. China
Chung-kuan Cheng, Univ. of California, San Diego
pp. 628-633
W-L. Hung, The Pennsylvania State University, University Park, PA
Y. Xie, The Pennsylvania State University, University Park, PA
N. Vijaykrishnan, The Pennsylvania State University, University Park, PA
C. Addo-Quaye, The Pennsylvania State University, University Park, PA
T. Theocharides, The Pennsylvania State University, University Park, PA
M. J. Irwin, The Pennsylvania State University, University Park, PA
pp. 634-639
Srinivasa R. Sridhara, University of Illinois at Urbana Champaign
Naresh R. Shanbhag, University of Illinois at Urbana Champaign
Ganesh Balamurugan, Intel Corporation, Hillsboro OR
pp. 642-647
Sani R. Nassif, IBM Austin Research Laboratory, Austin, Texas
Zhuo Li, Texas A&M University, College Station, Texas
pp. 648-653
A. Zahabi, University of Tehran, Tehran, Iran
O. Shoaei, University of Tehran, Tehran, Iran
Y. Koolivand, University of Tehran, Tehran, Iran
pp. 662-667
Dinesh Patil, Stanford University, Stanford, CA
Sunghee Yun, Stanford University, Stanford, CA
Seung-Jean Kim, Stanford University, Stanford, CA
Alvin Cheung, Stanford University, Stanford, CA
Mark Horowitz, Stanford University, Stanford, CA
Stephen Boyd, Stanford University, Stanford, CA
pp. 676-681
Hao Yu, University of California, Los Angeles
Lei He, University of California, Los Angeles
pp. 682-687
A. Teene, LSI Logic Corporation, Fort Collins, CO
B. Davis, LSI Logic Corporation, Fort Collins, CO
R. Castagnetti, LSI Logic Corporation, Fort Collins, CO
J. Brown, LSI Logic Corporation, Fort Collins, CO
S. Ramesh, LSI Logic Corporation, Fort Collins, CO
pp. 694-699
Author Index (PDF)
pp. 701-704
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