- I
- ISQED
- 2005
- Sixth International Symposium on Quality of Electronic Design (ISQED'05)
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Sixth International Symposium on Quality of Electronic Design (ISQED'05) San Jose, California March 21-March 23 ISBN: 0-7695-2301-3 Table of Contents
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 | Tutorial I |
 | Tutorial II |
 | Session EP1 |
 | Plenary Session 1P |
 | Session 1A: Tools and Flows for Quality Design |
Sam Lo, Synopsys, Inc., Mountain View, CA pp. 28-34
Luo Chun, Southeast University, P.R. China
Yang Jun, Southeast University, P.R. China
Wu XuFan, Southeast University, P.R. China
Zhang Yu, Southeast University, P.R. China pp. 40-45
 | Session 1B: High Level Power/Noise Reduction Techniques |
Kee-Jong Kim, Purdue University, West Lafayette, IN; LG-Philips LCD, Korea pp. 59-64
 | Session 1C: Leakage and Dynamic Power Issues |
S. Sarkar, Indian Institute of Technology, India pp. 72-76
Hung C. Ngo, IBM Austin Research Laboratory, Austin, TX pp. 83-87
Rahul Rao, University of Michigan, Ann Arbor, MI
Kevin Nowka, Austin Research Laboratories, IBM, Austin, TX pp. 88-93
 | Session 1D: Poster Session |
Jin He, University of California, Berkeley, CA
Jane Xi, University of California, Berkeley, CA
Hui Wan, University of California, Berkeley, CA pp. 96-101
Carlo Roma, STMicroelectronics, Agrate Brianza, Milan, Italy
Marco Poles, STMicroelectronics, Agrate Brianza, Milan, Italy pp. 107-112
C. K. Tang, University of Arkansas, Fayetteville, AR
P. K. Lala, University of Arkansas, Fayetteville, AR pp. 128-132
Zhaojun Wo, University of Massachusetts, Amherst, MA pp. 137-142
Atsushi Kurokawa, Semiconductor Technology Academic Research Center (STARC); Waseda University
Hiroo Masuda, Semiconductor Technology Academic Research Center (STARC) pp. 153-158
Haixia Gao, Microelectronics Institute, Xidian University, China
Yintang Yang, Microelectronics Institute, Xidian University, China
Xiaohua Ma, Microelectronics Institute, Xidian University, China
Gang Dong, Microelectronics Institute, Xidian University, China pp. 159-163
Hua Xiang, IBM T.J. Watson Research Center, Yorktown Heights, NY pp. 181-186
B. Ngo, San Jose State University, CA
M. Pham, San Jose State University, CA
L. He, San Jose State University, CA pp. 187-192
B. Bartz, LSI Logic Corporation, Milpitas, CA
C. Monzel, LSI Logic Corporation, Milpitas, CA
A. Teene, LSI Logic Corporation, Milpitas, CA
S. Ramesh, LSI Logic Corporation, Milpitas, CA pp. 193-196
M. Welling, Southern Illinois University at Carbondale
H. Wang, Southern Illinois University at Carbondale pp. 202-207
Yuchun Ma, Tsinghua University, Beijing, China
Song Chen, Tsinghua University, Beijing, China pp. 213-219
 | ISQED Luncheon Speech |
 | Session 2A: Test Application and Cost Reduction |
E. Kalligeros, University of Patras, Greece; Research Academic Computer Technology Institute, Greece
D. Kaseridis, University of Patras, Greece; Research Academic Computer Technology Institute, Greece
D. Nikolos, University of Patras, Greece; Research Academic Computer Technology Institute, Greece pp. 226-231
G. Pani, Southern Illinois University Carbondale pp. 232-237
Yinhe Han, Chinese Academy of Sciences, Beijing; Graduate School of Chinese Academy of Sciences, Beijing
Yu Hu, Chinese Academy of Sciences, Beijing
Huawei Li, Chinese Academy of Sciences, Beijing; Graduate School of Chinese Academy of Sciences, Beijing
Xiaowei Li, Chinese Academy of Sciences, Beijing; Graduate School of Chinese Academy of Sciences, Beijing pp. 238-243
Ahmad A. Al-Yamani, Stanford University, Stanford, CA; LSI Logic Corporation, Milpitas, CA pp. 244-249
 | Session 2B: DFM and Physical Layout |
Xin Wang, Synopsys Inc., Mountain View, CA
Qing Su, Synopsys Inc., Mountain View, CA pp. 258-263
Jie Yang, University of Michigan at Ann Arbor pp. 270-275
 | Session 2C: Performance and Reliability Analysis for Yield Optimization |
Rahul Rao, University of Michigan, Ann Arbor, MI
Kevin Nowka, Austin Research Laboratories, IBM, Austin, TX pp. 284-290
 | Session 3A: Functional Verification and Test Generation |
 | Session 3B: Power Delivery and Distribution |
 | Session 3C: Quality System Level Design and Synthesis |
Y. Xie, Pennsylvania State University pp. 364-369
Y. Xie, Pennsylvania State University pp. 375-380
 | Session 4A: DFM for Circuit Design |
B. Huang, University of Maryland, College Park
J. Qin, University of Maryland, College Park
X. Zhang, University of Maryland, College Park
M. Talmor, University of Maryland, College Park
Z. Gur, University of Maryland, College Park pp. 382-389
Zeljko Zilic, Microelectronics and Computer Systems Laboratory, Canada pp. 390-395
 | Session 4B: Leakage and Reliability Management |
Keunwoo Kim, IBM T. J. Watson Research Center, Yorktown Heights, NY
Jae-Joon Kim, IBM T. J. Watson Research Center, Yorktown Heights, NY
Shih-Hsien Lo, IBM T. J. Watson Research Center, Yorktown Heights, NY
Rajiv V. Joshi, IBM T. J. Watson Research Center, Yorktown Heights, NY pp. 410-415
 | Session 4C: Analog Test and BIST |
Amit Laknaur, Southern Illinois University Carbondale, Carbondale, IL
Haibo Wang, Southern Illinois University Carbondale, Carbondale, IL pp. 434-439
 | Session EP2 |
 | Plenary Session 2P |
 | Session 5A: Design Methods and Tools in DSM |
Timwah Luk, Fairchild Semiconductor, South Portland, ME pp. 476-481
Youngsoo Shin, Korea Advanced Institute of Science and Technology, Republic of Korea pp. 482-487
 | Session 5B: Design Techniques for Leakage Reduction |
Xiaojun Li, University of Maryland, College Park, MD pp. 496-502
 | Session 5C: Variability Issues in Nanoscale Circuits |
Emad Hamadeh, Santa Clara University, CA; Applied Micro C. Co. (AMCC), Sunnyvale, CA
Iliya Pesic, Santa Clara University, CA; Silvaco International, Santa Clara, CA pp. 510-515
Yu Cao, University of California, Berkeley, CA
Jason Cain, University of California, Berkeley, CA
Ruth Wang, University of California, Berkeley, CA
Jan Rabaey, University of California, Berkeley, CA pp. 516-521
 | Session 6A: Issues in Noise and Timing |
Tao Lin, Magma Design Automation, Santa Clara, CA pp. 536-541
Zhenyu Qi, University of California, Riverside
Hang Li, University of California, Riverside
Lifeng Wu, Cadence Design Systems Inc. San Jose, CA
Yici Cai, Tsinghua University, Beijing, China pp. 542-547
 | Session 6B: Design Approaches for System in Package (SiP) |
Anru Wang, University of California, Santa Cruz
Wayne Dai, University of California, Santa Cruz pp. 562-566
Meigen Shen, Royal Institute of Technology (KTH), Sweden pp. 573-578
 | Session 6C: DSM Interconnect Issues |
Martin DF Wong, University of Illinois at Urbana-Champaign, Urbana, IL pp. 580-585
Jiaxing Sun, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China
Yun Zheng, CEC Huada Electronic Design Co., Ltd., Beijing, China
Qing Ye, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China
Tianchun Ye, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China pp. 598-602
Pu Liu, University of California, Riverside, CA
Zhenyu Qi, University of California, Riverside, CA pp. 603-608
 | Session 7A: Advances in Floor Planning |
Hua Xiang, IBM T.J. Watson Research Center, Yorktown Heights, NY
I-Min Liu, Cadence Design System, San Jose, CA pp. 622-627
W-L. Hung, The Pennsylvania State University, University Park, PA
Y. Xie, The Pennsylvania State University, University Park, PA
C. Addo-Quaye, The Pennsylvania State University, University Park, PA
M. J. Irwin, The Pennsylvania State University, University Park, PA pp. 634-639
 | Session 7B: Issues in On-Chip Communication and Analog/RF Designs |
Zhuo Li, Texas A&M University, College Station, Texas pp. 648-653
A. Zahabi, University of Tehran, Tehran, Iran
O. Shoaei, University of Tehran, Tehran, Iran pp. 662-667
 | Session 7C: Robust Design under Parameter Variations |
Hao Yu, University of California, Los Angeles
Lei He, University of California, Los Angeles pp. 682-687
Wei Ling, Ecole Polytechnique de Montreal, Canada pp. 688-693
A. Teene, LSI Logic Corporation, Fort Collins, CO
B. Davis, LSI Logic Corporation, Fort Collins, CO
J. Brown, LSI Logic Corporation, Fort Collins, CO
S. Ramesh, LSI Logic Corporation, Fort Collins, CO pp. 694-699 Usage of this product signifies your acceptance of the Terms of Use.
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