With IC technology scaling down to nanometer, the higher working frequency and smaller geometry drive the reliability of signal interconnects to be a critical challenge in VLSI design. The post-layout reliability verification is an effective solution to this challenge. However, the implementation of a full-chip verification on signal electro-migration requires huge amounts of interconnect current calculation. The dynamic current calculation methods established on time domain circuit simulators are prohibitively expensive of runtime when applied to DSM ICs. Therefore, in this paper, we propose an efficient static current calculation technique. One of distinguished characteristics of this technique is that current calculations are based on ramp input signals, the more realistic signal than the step input. Moreover, an advanced gate model is applied to this technique, thus the current it yields is more accurate than that using switch-resistor model. Since different electromigration models require different types of interconnect current values in their evaluations, this technique can handle the calculation on average, RMS and peak current in order to perform a comprehensive reliability validation in IC designs. The experimental results demonstrate its efficiency and accuracy of this technique. Combined with the pruning technique, it is also integrated into a reliability verification flow to be tested on a SoC design.