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Sixth International Symposium on Quality of Electronic Design (ISQED'05)
Power Grid Planning for Microprocessors and SOCS
San Jose, California
March 21-March 23
ISBN: 0-7695-2301-3
| ASCII Text | x | ||
| Qing K. Zhu, David Ayers, "Power Grid Planning for Microprocessors and SOCS," Quality Electronic Design, International Symposium on, pp. 352-356, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005. | |||
| BibTex | x | ||
| @article{ 10.1109/ISQED.2005.95, author = {Qing K. Zhu and David Ayers}, title = {Power Grid Planning for Microprocessors and SOCS}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2301-3}, pages = {352-356}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.95}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Quality Electronic Design, International Symposium on TI - Power Grid Planning for Microprocessors and SOCS SN - 0-7695-2301-3 SP352 EP356 A1 - Qing K. Zhu, A1 - David Ayers, PY - 2005 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.95
This paper describes power grid planning methodology for high-performance microprocessors and SOC chips. It shows how to estimate currents from an existing chip to a new chip. The power grid planning and pre-layout simulation becomes important for time to market of chip design. We will discuss the current scaling technique and one SOC design example. More details on the methodology can be found in [Power Distribution Network Design for VLSI].
Citation:
Qing K. Zhu, David Ayers, "Power Grid Planning for Microprocessors and SOCS," isqed, pp.352-356, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005
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