Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture

Atsushi Kurokawa; Tetsuro Kage; Yasuaki Inoue; Masaharu Yamamoto; Nobuto Ono; Hiroo Masuda

doi:10.1109/ISQED.2005.29

I
ISQED
2005
Sixth International Symposium on Quality of Electronic Design (ISQED'05)
Abstract - Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture

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Sixth International Symposium on Quality of Electronic Design (ISQED'05)

Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture

San Jose, California

March 21-March 23

ISBN: 0-7695-2301-3

	ASCII Text	x
	Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda, "Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture," Quality Electronic Design, International Symposium on, pp. 153-158, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005.

	BibTex	x
	@article{ 10.1109/ISQED.2005.29, author = {Atsushi Kurokawa and Masaharu Yamamoto and Nobuto Ono and Tetsuro Kage and Yasuaki Inoue and Hiroo Masuda}, title = {Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2301-3}, pages = {153-158}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.29}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture SN - 0-7695-2301-3 SP153 EP158 A1 - Atsushi Kurokawa, A1 - Masaharu Yamamoto, A1 - Nobuto Ono, A1 - Tetsuro Kage, A1 - Yasuaki Inoue, A1 - Hiroo Masuda, PY - 2005 KW - null VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Atsushi Kurokawa, Semiconductor Technology Academic Research Center (STARC); Waseda University

Masaharu Yamamoto, Semiconductor Technology Academic Research Center (STARC)

Nobuto Ono, Jedat Innovation Inc.

Tetsuro Kage, Tokyo National College of Technology

Yasuaki Inoue, Waseda University

Hiroo Masuda, Semiconductor Technology Academic Research Center (STARC)

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2005.29

In the VLSI design of sub-100-nm technologies, most engineers in the process, chip-design, and EDA areas are acutely aware of a tough "Red Brick Wall" emerging because of process variability and physical integrity issues. Process variability is not only a fabrication problem, but also a serious design issue. Similarly, physical integrity problems are not only design and EDA issues, but also process-related architecture problems.

In this paper, we investigate the practicality of a dense power-ground interconnect architecture developed to ensure physical design integrity. The interconnect architecture basically consists of adjoining power and ground lines. We describe the design methodologies and a simple method for calculating the decoupling capacitance (decap) values, and report both calculated and measured decap values for the architecture. We also report measurement results regarding the signal line capacitance and the interconnect defect-type yield of a 90-nm process technology.

Citation:

Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda, "Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture," isqed, pp.153-158, Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005

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