- I
- ISQED
- 2004
- 5th International Symposium on Quality Electronic Design (ISQED'04)
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5th International Symposium on Quality Electronic Design (ISQED'04) San Jose, California March 22-March 24 ISBN: 0-7695-2093-6 Table of Contents
 | Introduction |
 | ISQED Tutorials: Compact Modeling and Analysis for Nanometer-Scale CMOS Design |
 | ISQED Panel Discussion EP1 |
 | Plenary Session I |
 | Session 1A: Physical Design Migration |
 | Session 1B: CMOS Device and Memory |
Jin He, University of California at Berkeley
Xuemei Xi, University of California at Berkeley
Mansun Chan, Hong Kong University of Science and Technology pp. 45-50
Yu Cao, University of California at Berkeley pp. 55-60
 | Session 1C: Poster Session |
Lei He, University of California at Los Angeles pp. 69-74
E. Kursun, University of California at Los Angeles
S. Ghiasi, University of California at Los Angeles pp. 116-121
Sunil Yu, Santa Clara University and KAIST pp. 122-125
 | ISQED Luncheon Speech |
 | Session 2A: Topics in Printability |
 | Session 2B: Package Design and Interaction |
 | Session 2C: Test Generation and Application |
M. Bellos, University of Patras and Research Academic Computer Technology Institute
D. Bakalis, University of Patras and Research Academic Computer Technology Institute
D. Nikolos, University of Patras and Research Academic Computer Technology Institute pp. 205-210
J. Sosa, University of Las Palmas de Gran Canaria
H. Navarro, University of Las Palmas de Gran Canaria pp. 217-222
 | Session 3A: Modeling and Simulations of Electromigration and Eletromagnetic Effect |
Rob Sharpe, Lawrence Livermore National Laboratory pp. 244-249
 | Session 3B: Interconnect: Capacitance Extraction and Delay Calculation |
Ye Liu, Shanghai Jiao Tong University
Mei Xue, Shanghai Jiao Tong University pp. 271-275
 | Session 3C: Substrate Noise: Analysis and Prevention |
 | ISQED Panel Discussion EP2 |
Ron Wilson, EE Times (CMP Media Electronics Group) pp. 317-319
 | Plenary Session II |
 | Session 4A: Interconnect Delay and Coupling |
 | Session 4B: Analysis of Variations |
 | Session 4C: Layout and Design Techniques for Quality and Reliability |
 | Session 5A: Analog Testing |
 | Session 5B: Low Power Design |
Man L Mui, University of Illinois at Urbana-Champaign pp. 409-414
Ge Yang, University of California at Santa Cruz pp. 421-424
 | Session 5C: ESD |
Wen-Yu Lo, Silicon Intergrated Systems (SiS) Corp. pp. 433-438
 | Session 6A: DFM Design Techniques |
Steffen R?, Fraunhofer Institute for Integrated Circuits/EAS, Zeunerstr pp. 478-482
 | Session 6B: Delay Test Issues |
Y. Xie, Pennsylvania State University pp. 503-508
 | Session 6C: Circuit Design Trends in DSM |
Ji Luo, University of Maryland at College Park
Hu Huang, University of Maryland at College Park pp. 522-527
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