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International Symposium on Quality Electronic Design (ISQED '01)
San Jose, California
March 26-March 28
ISBN: 0-7695-1025-6
Table of Contents
ISQED Tutorials
Tutorial Track A
Tutorial A1: System-on-Chip: Embedded Test Strategies
Tutorial A2: Design and Test of Low Voltage CMOS Circuits
Tutorial A3: Redundancy Requirements for Embedded Memories
Tutorial Track B
Tutorial B1: Design Metrics to Achieve Design Quality
Tutorial B2: Fundamental Methods to Enable SoC Design and Reuse
Tutorial B3: Issues in Deep Submicron State-of-the-Art ESD Design
Tutorial Track C
Tutorial C1: Application of Formal Verification to Design Creation and Implementation
Tutorial C2: Verification and Validation of Complex Digital Systems: An Industrial Perspective
Tutorial C3: Physical Verification at 0.13 Micron and Below
Tutorial Track D
Tutorial D1: Re-Connecting MOS Modeling and Circuit Design: New Methods for Design Quality
Tutorial D2: Interconnect Modeling for Timing, Signal Integrity and Reliability
Tutorial D3: On-Chip Inductance Extraction and Modeling
Evening Panel Discussion: The 50-Million Transistor Chip: The Quality Challenge for 2001
Plenary Session I
Session 1A: Impact of Verification on Complex SOC Quality
Amjad Hajjar, Colorado State University
Tom Chen, Colorado State University
Isabelle Munn, Colorado State University
Anneliese Andrews, Colorado State University
Maria Bjorkman, Colorado State University
pp. 31
F. Sforza, STMicroelectronics
L. Battù, STMicroelectronics
M. Brunelli, STMicroelectronics
A. Castelnuovo, STMicroelectronics
M. Magnaghi, STMicroelectronics
pp. 50
Session 1B: Quality of EDA Tools and Design Methodologies
Gulsun Yasar, IBM Microelectronics Division
Charles Chiu, IBM Microelectronics Division
Robert A. Proctor, IBM Microelectronics Division
James P. Libous, IBM Microelectronics Division
pp. 71
Session 1C: Design, Fabrication and Reliability Challenges for Emerging Technologies
Sheldon Wu, Taiwan Semiconductor Manufacturing Company
Fred Wang, Taiwan Semiconductor Manufacturing Company
Lie-Szu Juang, Taiwan Semiconductor Manufacturing Company
pp. 111
Session 2A: Capacitive Crosstalk Analysis
Andrew B. Kahng, UCSD CSE and ECE Departments
Sudhakar Muddu, Sanera Systems, Inc.
Niranjan Pol, Cadence Design Systems, Inc.
Devendra Vidhani, SUN Microsystems, Inc.
pp. 145
Murat R. Becer, Motorola Inc.
David Blaauw, Motorola Inc.
Supamas Sirichotiyakul, Motorola Inc.
Chanhee Oh, Motorola Inc.
Vladimir Zolotov, Motorola Inc.
Jingyan Zuo, Motorola Inc.
Rafi Levy, Motorola Semiconductor Israel Ltd.
Ibrahim N. Hajj, University of Illinois at Urbana-Champaign
pp. 158
Session 2B: Interconnect Modeling and Analysis
Yusuke Nakashima, The University of Tokyo
Makoto Ikeda, The University of Tokyo
Kunihiro Asada, The University of Tokyo
pp. 179
Yu Cao, University of California, at Berkeley
Xuejue Huang, University of California, at Berkeley
Chenming Hu, University of California, at Berkeley
Norman Chang, Hewlett-Packard Laboratories
Shen Lin, Hewlett-Packard Laboratories
O. Sam Nakagawa, Hewlett-Packard Laboratories
Weize Xie, Hewlett-Packard Laboratories
pp. 185
Session 2C: Power-Aware Design
Wei-Chung Cheng, University of Southern California
Massoud Pedram, University of Southern California
pp. 199
G. Bai, University of Illinois at Urbana-Champaign
S. Bobba, University of Illinois at Urbana-Champaign
I.N. Hajj, University of Illinois at Urbana-Champaign
pp. 205
Zhenyu Tang, Univ. of Wisconsin
Lei He, Univ. of Wisconsin
Norman Chang, Hewlett-Packard Laboratories
Shen Lin, Hewlett-Packard Laboratories
Weize Xie, Hewlett-Packard Laboratories
Sam Nakagawa, Hewlett-Packard Laboratories
pp. 211
J.A. Montiel-Nelson, University of Las Palmas de Gran Canaria.
V de ARMAS, University of Las Palmas de Gran Canaria.
R. Sarmiento, University of Las Palmas de Gran Canaria.
And A. Nunez, University of Las Palmas de Gran Canaria.
pp. 223
Evening Panel Discussion: 0.13 micron: Will the Speed Bumps Slow the Race to Market?
Plenary Session II
Session D: Ph.D. Student Forum
Session E: Poster Session
Ming-Dou Ker, National Chiao-Tung University,
Wen-Yu Lo, National Chiao-Tung University,
Tung-Yang Chen, National Chiao-Tung University,
Howard Tang, United Microelectronics Corporation (UMC)
S.-S. Chen, United Microelectronics Corporation (UMC)
M.-C. Wang, United Microelectronics Corporation (UMC)
pp. 267
Wei Li, University of Central Florida
Qiang Li, University of Central Florida
J.S. Yuan, University of Central Florida
Joshua McConkey, University of Central Florida
Yuan Chen, Bell Laboratories
Sundar Chetlur, Bell Laboratories
Jonathan Zhou, Bell Laboratories
A.S. Oates, Bell Laboratories
pp. 284
Imed Ben Dhaou, Royal Institute of Technology
Hannu Tenhunen, Royal Institute of Technology
Vijay Sundararajan, University of Minnesota
Keshab K. Parhi, University of Minnesota
pp. 319
Mihaela Radu, Technical University of Cluj-Napoca
Dan Pitica, Technical University of Cluj-Napoca
Radu Munteanu, Technical University of Cluj-Napoca
Cristian Posteuca, Technical University of Cluj-Napoca
pp. 331
D. Bakalis, Computer Technology Institute
D. Nikolos, Computer Technology Institute
H. T. Vergos, Computer Technology Institute
X. Kavousianos, University of Patras
pp. 350
Session 3A: Defect Analysis and Test Generation
W. Kuzmicz, Warsaw University of Technology
W. Pleskacz, Warsaw University of Technology
J. Raik, Tallinn Technical University
R. Ubar, Tallinn Technical University
pp. 365
Chien-Nan Jimmy Liu, National Chiao Tung University
Chia-Chih Yen, National Chiao Tung University
Jing-Yang Jou, National Chiao Tung University
pp. 372
M. Michael, Southern Illinois University
S. Tragoudas, Southern Illinois University
pp. 384
Session 3B: Design of Programmable and Platform-Based IP
Rafael Peset Llopis, Philips Research Laboratories
Marcel Oosterhuis, Philips Research Laboratories
Sethuraman Ramanathan, Philips Research Laboratories
Paul Lippens, Philips Research Laboratories
Albert Van der Werf, Philips Research Laboratories
Steffen Maul, Philips Research Laboratories
Jim Lin, Philips Research Laboratories
pp. 393
Martin Speitel, Fraunhofer Institute for Integrated Circuits
Michael Schlicht, Fraunhofer Institute for Integrated Circuits
Martin Leyh, Fraunhofer Institute for Integrated Circuits
pp. 399
Chih-Yuan Chen, Industrial Technology Research Institute
Shing-Wu Tung, Industrial Technology Research Institute
pp. 405
Kazimierz Wiatr, AGH Technical University of Cracow
Ernest Jamro, AGH Technical University of Cracow
pp. 415
Session 3C: Embedded Panel Discussion: Consequences of Technology: What is the Impact of Electronic Design on the Quality of Life?
Session 4A: Design for Manufacturability
Anne Gattiker, IBM Austin Research Lab
Sani Nassif, IBM Austin Research Lab
Rashmi Dinakar, Rensselaer Polytechnic Institute
Chris Long, Sematech
pp. 437
Tae-Jin Kwon, SAMSUNG Electronics Co., Ltd.
Sang-Hoon Lee, SAMSUNG Electronics Co., Ltd.
Tae-Seon Kim, SAMSUNG Electronics Co., Ltd.
Hoe-Jin Lee, SAMSUNG Electronics Co., Ltd.
Young-Kwan Park, SAMSUNG Electronics Co., Ltd.
Taek-Soo Kim, SAMSUNG Electronics Co., Ltd.
Seok-Jin Kim, SAMSUNG Electronics Co., Ltd.
Jeong-Taek Kong, SAMSUNG Electronics Co., Ltd.
pp. 443
Session 4B: Embedded Memories
P. Daglio, STMicroelectronics N.V.
M. Araldi, STMicroelectronics N.V.
M. Morbarigazzi, STMicroelectronics N.V.
C. Roma, STMicroelectronics N.V.
pp. 451
K. Tatas, Democritus University of Thrace
A. Argyriou, Democritus University of Thrace
M. Dasigenis, Democritus University of Thrace
D. Soudris, Democritus University of Thrace
N. Zervas, University of Patras
pp. 456
Nai-Yin Sung, Taiwan Semiconductor Manufacturing Company Ltd.
Tsung-Yi Wu, Taiwan Semiconductor Manufacturing Company Ltd.
pp. 462
Session 4C: Device Modeling and Design Quality
Stefano Zanella, Universita degli Studi di Padova
Andrea Neviani, Universita degli Studi di Padova
Enrico Zanoni, Universita degli Studi di Padova
Paolo Miliozzi, Conexant Systems Inc.
Edoardo Charbon, Cadence Design Systems Inc.
Carlo Guardiani, PDF Solutions Inc.
Luca Carloni, University of California Berkeley
Alberto Sangiovanni-Vincentelli, University of California Berkeley
pp. 488
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