- I
- ISQED
- 2001
- International Symposium on Quality Electronic Design (ISQED '01)
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| | | | Bibliographic References | | | |
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International Symposium on Quality Electronic Design (ISQED '01) San Jose, California March 26-March 28 ISBN: 0-7695-1025-6 Table of Contents
 | Tutorial A1: System-on-Chip: Embedded Test Strategies |
| Tutorial A2: Design and Test of Low Voltage CMOS Circuits |
| Tutorial A3: Redundancy Requirements for Embedded Memories |
| Tutorial B1: Design Metrics to Achieve Design Quality |
| Tutorial B2: Fundamental Methods to Enable SoC Design and Reuse |
| Tutorial B3: Issues in Deep Submicron State-of-the-Art ESD Design |
| Tutorial C1: Application of Formal Verification to Design Creation and Implementation |
| Tutorial C2: Verification and Validation of Complex Digital Systems: An Industrial Perspective |
| Tutorial C3: Physical Verification at 0.13 Micron and Below |
| Tutorial D1: Re-Connecting MOS Modeling and Circuit Design: New Methods for Design Quality |
| Tutorial D2: Interconnect Modeling for Timing, Signal Integrity and Reliability |
| Tutorial D3: On-Chip Inductance Extraction and Modeling |
| Evening Panel Discussion: The 50-Million Transistor Chip: The Quality Challenge for 2001 |
| Plenary Session I |
| Session 1A: Impact of Verification on Complex SOC Quality |
| Session 1B: Quality of EDA Tools and Design Methodologies |
| Session 1C: Design, Fabrication and Reliability Challenges for Emerging Technologies |
Sheldon Wu, Taiwan Semiconductor Manufacturing Company
Fred Wang, Taiwan Semiconductor Manufacturing Company pp. 111
| Session 2A: Capacitive Crosstalk Analysis |
Rafi Levy, Motorola Semiconductor Israel Ltd. pp. 158
| Session 2B: Interconnect Modeling and Analysis |
Yu Cao, University of California, at Berkeley pp. 185
| Session 2C: Power-Aware Design |
G. Bai, University of Illinois at Urbana-Champaign
S. Bobba, University of Illinois at Urbana-Champaign
I.N. Hajj, University of Illinois at Urbana-Champaign pp. 205
V de ARMAS, University of Las Palmas de Gran Canaria. pp. 223
| Evening Panel Discussion: 0.13 micron: Will the Speed Bumps Slow the Race to Market? |
| Plenary Session II |
| Session D: Ph.D. Student Forum |
| Session E: Poster Session |
S.-S. Chen, United Microelectronics Corporation (UMC)
M.-C. Wang, United Microelectronics Corporation (UMC) pp. 267
Wei Li, University of Central Florida pp. 284
| Session 3A: Defect Analysis and Test Generation |
M. Renovell, Universit? de Montpellier II: Sciences et Techniques du Languedoc pp. 359
J. Raik, Tallinn Technical University
R. Ubar, Tallinn Technical University pp. 365
| Session 3B: Design of Programmable and Platform-Based IP |
Jim Lin, Philips Research Laboratories pp. 393
Martin Leyh, Fraunhofer Institute for Integrated Circuits pp. 399
| Session 3C: Embedded Panel Discussion: Consequences of Technology: What is the Impact of Electronic Design on the Quality of Life? |
| Session 4A: Design for Manufacturability |
| Session 4B: Embedded Memories |
K. Tatas, Democritus University of Thrace pp. 456
Nai-Yin Sung, Taiwan Semiconductor Manufacturing Company Ltd.
Tsung-Yi Wu, Taiwan Semiconductor Manufacturing Company Ltd. pp. 462
| Session 4C: Device Modeling and Design Quality | Usage of this product signifies your acceptance of the Terms of Use.
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