Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation

Yoshitaka Murasaka; Takashi Morie; Atsushi Iwata; Makoto Nagata; Takafumi Ohmoto

doi:10.1109/ISQED.2001.915275

I
ISQED
2001
International Symposium on Quality Electronic Design (ISQED '01)
Abstract - Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/EndNote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Yoshitaka Murasaka Articles by Makoto Nagata Articles by Takafumi Ohmoto Articles by Takashi Morie Articles by Atsushi Iwata

International Symposium on Quality Electronic Design (ISQED '01)

Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation

San Jose, California

March 26-March 28

ISBN: 0-7695-1025-6

	ASCII Text	x
	Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata, "Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation," Quality Electronic Design, International Symposium on, pp. 482, International Symposium on Quality Electronic Design (ISQED '01), 2001.

	BibTex	x
	@article{ 10.1109/ISQED.2001.915275, author = {Yoshitaka Murasaka and Makoto Nagata and Takafumi Ohmoto and Takashi Morie and Atsushi Iwata}, title = {Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2001}, isbn = {0-7695-1025-6}, pages = {482}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915275}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Quality Electronic Design, International Symposium on TI - Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation SN - 0-7695-1025-6 SP EP A1 - Yoshitaka Murasaka, A1 - Makoto Nagata, A1 - Takafumi Ohmoto, A1 - Takashi Morie, A1 - Atsushi Iwata, PY - 2001 VL - 0 JA - Quality Electronic Design, International Symposium on ER -

Yoshitaka Murasaka, Hiroshima University

Makoto Nagata, Hiroshima University

Takafumi Ohmoto, Hiroshima University

Takashi Morie, Hiroshima University

Atsushi Iwata, Hiroshima University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915275

Fundamental matrix (F-matrix) based substrate mesh reduction technique is incorporated in a chip-level substrate noise simulation methodology. A system-level equivalent circuit model of a 0.6-?m CMOS substrate noise evaluation chip demonstrates simulation errors of less than 15% by comparing it with 100-ps 100-?V substrate noise wave-form measurements.

Citation:

Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata, "Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation," isqed, pp.482, International Symposium on Quality Electronic Design (ISQED '01), 2001

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.