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International Symposium on Quality Electronic Design (ISQED '01)
Energy Efficient Signaling in Deep Submicron CMOS Technology
San Jose, California
March 26-March 28
ISBN: 0-7695-1025-6
| ASCII Text | x | ||
| Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi, "Energy Efficient Signaling in Deep Submicron CMOS Technology," Quality Electronic Design, International Symposium on, pp. 319, International Symposium on Quality Electronic Design (ISQED '01), 2001. | |||
| BibTex | x | ||
| @article{ 10.1109/ISQED.2001.915250, author = {Imed Ben Dhaou and Hannu Tenhunen and Vijay Sundararajan and Keshab K. Parhi}, title = {Energy Efficient Signaling in Deep Submicron CMOS Technology}, journal ={Quality Electronic Design, International Symposium on}, volume = {0}, year = {2001}, isbn = {0-7695-1025-6}, pages = {319}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2001.915250}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Quality Electronic Design, International Symposium on TI - Energy Efficient Signaling in Deep Submicron CMOS Technology SN - 0-7695-1025-6 SP EP A1 - Imed Ben Dhaou, A1 - Hannu Tenhunen, A1 - Vijay Sundararajan, A1 - Keshab K. Parhi, PY - 2001 VL - 0 JA - Quality Electronic Design, International Symposium on ER - | |||
In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeaters insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeaters insertion. VIJIM algorithm has been implemented to design a robust inverter chain for on-chip signaling using 0:25μm, 2.5V,6metal layers CMOS process. An average of 70% of energy-saving has been achieved by reducing the supply voltage from 2.5V down to 1.5V.
Citation:
Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi, "Energy Efficient Signaling in Deep Submicron CMOS Technology," isqed, pp.319, International Symposium on Quality Electronic Design (ISQED '01), 2001
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