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2009 Eighth International Symposium on Parallel and Distributed Computing
Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric
Lisbon, Portugal
June 30-July 04
ISBN: 978-0-7695-3680-4
| ASCII Text | x | ||
| Muhammad Mukaram Khan, Javier Navaridas Palma, Alexander D. Rast, Xin Jin, Luis A. Plana, Mikel Luján, John Viv Woods, Jose Miguel-Alonso, Steve B. Furber, "Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric," Parallel and Distributed Computing, International Symposium on, pp. 54-61, 2009 Eighth International Symposium on Parallel and Distributed Computing, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/ISPDC.2009.25, author = {Muhammad Mukaram Khan and Javier Navaridas Palma and Alexander D. Rast and Xin Jin and Luis A. Plana and Mikel Luján and John Viv Woods and Jose Miguel-Alonso and Steve B. Furber}, title = {Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric}, journal ={Parallel and Distributed Computing, International Symposium on}, volume = {0}, year = {2009}, isbn = {978-0-7695-3680-4}, pages = {54-61}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISPDC.2009.25}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Parallel and Distributed Computing, International Symposium on TI - Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric SN - 978-0-7695-3680-4 SP54 EP61 A1 - Muhammad Mukaram Khan, A1 - Javier Navaridas Palma, A1 - Alexander D. Rast, A1 - Xin Jin, A1 - Luis A. Plana, A1 - Mikel Luján, A1 - John Viv Woods, A1 - Jose Miguel-Alonso, A1 - Steve B. Furber, PY - 2009 KW - Chip Multiprocessor KW - Neural Networks KW - Multi-CMP Configuration KW - Massively Parallel Computing KW - Fault-tolerance KW - Real-time Application KW - Embedded Systems VL - 0 JA - Parallel and Distributed Computing, International Symposium on ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISPDC.2009.25
Configuring a million-core parallel system at boot time is a difficult process when the system has neither specialised hardware support for the configuration process nor a preconfigured default state that puts it in operating condition. SpiNNaker is a parallel Chip Multiprocessor (CMP) system for neural network (NN) simulation. Where most large CMP systems feature a sideband network to complete the boot process, SpiNNaker has a single homogeneous network interconnect for both application inter-processor communications and system control functions such as boot load and run-time user-system interaction. This network improves fault tolerance and makes it easier to support dynamic run-time reconfiguration, however, it requires a boot process that is transaction-level compatible with the application’s communications model. Since SpiNNaker uses event-driven asynchronous communications throughout, theloader operates with purely local control: there is no global synchronisation, state information, or transition sequence. A novel two-stage “unfolding” boot-up process efficiently configures the SpiNNaker hardware and loads the application using a high-speed flood-fill technique with support for run-time re-configuration. SystemC simulation of a multi-CMP SpiNNaker system indicates an error-free CMP configuration time of 1.3ms, while a high-level simulation of a full-scale system (64K CMPs) indicates a mean application-loading time of ∼20ms (for a 100KB application), which is virtually independent of the sizeof the system. We verified the CMP configuration process with hardware-level Verilog simulation.
Index Terms:
Chip Multiprocessor, Neural Networks, Multi-CMP Configuration, Massively Parallel Computing, Fault-tolerance, Real-time Application, Embedded Systems
Citation:
Muhammad Mukaram Khan, Javier Navaridas Palma, Alexander D. Rast, Xin Jin, Luis A. Plana, Mikel Luján, John Viv Woods, Jose Miguel-Alonso, Steve B. Furber, "Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric," ispdc, pp.54-61, 2009 Eighth International Symposium on Parallel and Distributed Computing, 2009
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