2000 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS (Cat. No.00EX422)

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Performance analysis through synthetic trace generation (Abstract)

L. Eeckhout, Dept. of Electron. & Inf. Syst., Ghent Univ., Belgium

K. de Bosschere

H. Neefs

pp. 1-6

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Extracting fine-grain profiles of in-order executions of instruction level parallel programs (Abstract)

N. Zingirian, Dipt. di Elettronica e Inf., Padova Univ., Italy

H. Maresca

pp. 7-12

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Accurate simulation and evaluation of code reordering (Abstract)

J. Kalamatianos, Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA

D.R. Kaeli

pp. 13-20

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Quantifying instruction-level parallelism limits on an EPIC architecture (Abstract)

Hsien-Hsin Lee, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

Youfeng Wu

G. Tyson

pp. 21-27

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Performance evaluation of real-time scheduling on a multicomputer architecture (Abstract)

L.F. Friedrich, Dept. de Inf. e de Estatistica, Univ. Federal de Santa Catarina, Florianopolis, Brazil

pp. 28-33

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Performance evaluation of middleware bridging technologies (Abstract)

R. Fatoohi, Comput. Eng., San Jose State Univ., CA, USA

V. Gunwani

Qi Wang

C. Zheng

pp. 34-39

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A practitioner report on the evaluation of the performance of the C, C++ and Java compilers on the OS/390 platform (Abstract)

D.A. Cargill, Toronto Lab., IBM Canada Ltd., North York, Ont., Canada

M. Radaideh

pp. 40-45

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DB2 for OS/390 V5 vs. V6 outer join performance (Abstract)

M. Weihrauch, Santa Teresa Lab., IBM, San Jose, CA, USA

pp. 46-51

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Checking order-insensitivity using ternary simulation in synchronous programs (Abstract)

M. Yeddes, INPG, Univ. Joseph Fourier, St. Martin d'Heres, France

H. Alla

pp. 52-57

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Do generational schemes improve the garbage collection efficiency? (Abstract)

W. Srisa-an, Dept. of Comput. Sci., Illinois Inst. of Technol., Chicago, IL, USA

J.M. Chang

pp. 58-63

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A quantitative simulator for dynamic memory managers (Abstract)

J.M. Chang, Dept. of Comput. Sci., Illinois Inst. of Technol., Chicago, IL, USA

W. Srisa-An

J.M. Chang

pp. 64-69

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Real-time image on QoS Web (Abstract)

Hong Liu, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Dartmouth, MA, USA

Hongdu Fang

pp. 70-75

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Issues in the design of store buffers in dynamically scheduled processors (Abstract)

R. Bhargava, Lab. for Comput. Archit., Texas Univ., Austin, TX, USA

L.K. John

pp. 76-87

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Performance tradeoffs in sequencer design on a new G4 PowerPC/sup TM/ microprocessor (Abstract)

L.K. John, Somerset Design Center, Motorola Inc., Austin, TX, USA

D. Holloway

pp. 88-94

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Instruction overhead and data locality effects in superscalar processors (Abstract)

M. Annavaram, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

G.S. Tyson

E.S. Davidson

pp. 95-100

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Modeling load address behaviour through recurrences (Abstract)

L. Ramos, Dept. Inf. e Ingenieria de Sistemas, Zaragoza Univ., Spain

pp. 101-108

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Methodology to optimize the cost/performance of disk subsystems (Abstract)

R. Recio, IBM Corp., Austin, TX, USA

W.T. Boyd

pp. 109-115

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Invocation profile characterization of Java applications (Abstract)

A. Barisone, Dept. of Electron. & Biophys. Eng., Genoa Univ., Italy

pp. 116-122

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Some observations based on simple models of MP scaling (Abstract)

E. Kronstadt, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

pp. 123-128

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Performance scalability in multiprocessor systems with resource contention (Abstract)

S. Majumdar, Dept. of Syst. & Comput. Eng., Carleton Univ., Ottawa, Ont., Canada

pp. 129-138

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An efficient solver for Cache Miss Equations (Abstract)

N. Bermudo, Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain

X. Vera

A. Gonzalez

J. Llosa

pp. 139-145

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An analytical model for loop tiling and its solution (Abstract)

V. Sarkar, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

N. Megiddo

pp. 146-153

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CommBench-a telecommunications benchmark for network processors (Abstract)

T. Wolf, Dept. of Comput. Sci. & Electr. Eng., Washington Univ., St. Louis, MO, USA

M. Franklin

pp. 154-162

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Simplified workload characterization using unified prediction (Abstract)

K. Driesen, Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada

Feng Ji

C. Kwan

pp. 163-171

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A new approach in the analysis and modeling of disk access patterns (Abstract)

M.E. Gomez, Dept. de Sistemas Inf. y Comput., Univ. Politecnica de Valencia, Spain

V. Santonja

pp. 172-177

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Mobile functionality in a pervasive world (Abstract)

J. Jagiello, Dept. of Defence, Defence Sci. & Technol. Organ., Canberra, ACT, Australia

N. Tay

B. Biddington

R. Dacray

pp. 178-183

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Design alternatives for scalable Web server accelerators (Abstract)

Junehwa Song, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

E. Levy-Abegnoli

A. Iyengar

D. Dias

pp. 184-192

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Web latency reduction via client-side prefetching (Abstract)

A.N. Eden, Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

B.W. Joh

T. Mudge

pp. 193-200

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A server performance model for static Web workloads (Abstract)

K. Kant, Server Archit. Lab., Intel Corp., USA

C.R.M. Sundaram

pp. 201-206

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Author Index (Abstract)

pp. 207-207

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