May 7, 2008 to May 9, 2008
As System-on-Chip (SoCs) become more complex, highperformance interconnection mediums are required to handle their complexity. Network-on-Chips (NoCs) enable integration of more Intellectual Properties (IPs) into theSoC with increased performance. In the recent MARTE(Modeling and Analysis of Real-time and EmbeddedSystems) Profile, a notion of multidimensional multiplicity has been proposed to model repetitive structures and topologies. This paper presents a modeling methodology based on that notation to model the Delta Network family of Interconnection Networks for NoC construction.
SoC, NoC, MINs, Delta Networks, MARTE, MDE, UML2 Templates
Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser, "Using an MDE Approach for Modeling of Interconnection Networks", ISPAN, 2008, Parallel Architectures, Algorithms, and Networks, International Symposium on, Parallel Architectures, Algorithms, and Networks, International Symposium on 2008, pp. 289-294, doi:10.1109/I-SPAN.2008.40