CSDL - Proceedings I

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-viii

Message from the Symposium Chair (PDF)

pp. ix

Message from the Program Chair (PDF)

pp. x

Conference Committees (PDF)

pp. xi-xii

EDA to the Rescue of the Silicon Roadmap (PDF)

Thomas W. Williams

pp. 1

A Mature Methodology for Implementing Multi-Valued Logic in Silicon (Abstract)

Mark H. Nodine

Craig M. Files

pp. 2-7

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Design of High-Performance Quaternary Adders Based on Output-Generator Sharing (Abstract)

Hirokatsu Shirahama

Takahiro Hanyu

pp. 8-13

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Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices (Abstract)

pp. 14-19

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Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data (Abstract)

Yasushi Yuminaka

Yasunori Takahashi

pp. 20-25

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Betweenness, Metrics and Entropies in Lattices (Abstract)

Dan A. Simovici

pp. 26-31

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On Maximal Hyperclones on {0, 1} ? A New Approach (Abstract)

Hajime Machida

Jovanka Pantovic

pp. 32-37

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Majority and Other Polynomials in Minimal Clones (Abstract)

Hajime Machida

Tamas Waldhauser

pp. 38-43

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Comparative Study by Solving the Test Compaction Problem (Abstract)

Doina Logofatu

Rolf Drechsler

pp. 44-49

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Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators (Abstract)

Shinobu Nagayama

Tsutomu Sasao

pp. 50-56

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On the Complexity of Classification Functions (Abstract)

Tsutomu Sasao

pp. 57-63

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MDD with Added Null-Value and All-Value Edges (Abstract)

Craig M. Files

Mark H. Nodine

pp. 64-69

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High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit (Abstract)

pp. 70-75

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Permutations under Spectral Transforms (Abstract)

Claudio Moraga

pp. 76-81

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On Fixed Points and Cycles in the Reed Muller Domain (Abstract)

pp. 82-87

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A Galois Field Approach to Modelling Gene Expression Regulation (Abstract)

pp. 88-93

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On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults (Abstract)

Stephan Eggersgl?

Rolf Drechsler

pp. 94-99

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Deciding the Satisfiability of Propositional Formulas in Finitely-Valued Signed Logics (Abstract)

pp. 100-105

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Encoding Max-CSP into Partial Max-SAT (Abstract)

pp. 106-111

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High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language (Abstract)

pp. 112-117

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Semirigid Equivalence Relations on a Finite Set (Abstract)

pp. 118-123

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Foundations of Higher Radix Numeric Computation (PDF)

David W. Matula

pp. 124

Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram (Abstract)

pp. 125-130

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A Qualitative Modal Representation of Quantum Register Transformations (Abstract)

pp. 131-137

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On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams (Abstract)

pp. 138-143

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Superposed Quantum State Initialization Using Disjoint Prime Implicants (SQUID) (Abstract)

David J. Rosenbaum

Marek A. Perkowski

pp. 144-149

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Generalized Modus Ponens Based on Linguistic Modifiers in a Symbolic Multi-Valued Framework (Abstract)

Saoussen Bel Hadj Kacem

Amel Borgi

Khaled Ghedira

pp. 150-155

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Soft Computing Methods for Prediction of Replication Origins in Caudoviruses (Abstract)

Raul Cruz-Cano

Igor Aizenberg

pp. 156-162

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Default Reasoning with Imperfect Information in Multivalued Logics (Abstract)

Daniel Stamate

pp. 163-168

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Classification of Fastest Quaternary Linearly Independent Arithmetic Transforms (Abstract)

Bogdan J. Falkowski

Cheng Fu

pp. 169-173

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A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter (Abstract)

pp. 174-179

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Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells (Abstract)

Nobuaki Okada

Michitaka Kameyama

pp. 180-185

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Multiple Valued Logic Using 3-State Quantum Dot Gate FETs (Abstract)

John A. Chandy

Faquir C. Jain

pp. 186-190

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Projective Measurement-Based Logic Synthesis of Quantum Circuits (Abstract)

Martin Lukac

Marek Perkowski

pp. 191-196

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Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells (Abstract)

Theodore W. Manikas

Dale Teeters

pp. 197-201

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Quantum Logic Implementation of Unary Arithmetic Operations (Abstract)

pp. 202-207

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Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits (Abstract)

Mozammel H.A. Khan

pp. 208-213

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Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares (Abstract)

pp. 214-219

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RevLib: An Online Resource for Reversible Functions and Reversible Circuits (Abstract)

pp. 220-225

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Properties and Computational Algorithm for Fastest Quaternary Linearly Independent Transforms (Abstract)

pp. 226-231

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Hybrid Reed-Muller Haar Transform and its Application in Reduction the Spectral Representations of Logic Functions (Abstract)

pp. 232-237

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Remarks on Bandwidth and Regularities in Functions on Finite Non-Abelian Groups (Abstract)

Radomir S. Stankovic

Jaakko Astola

pp. 238-243

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Author Index (PDF)

pp. 244-245

Publisher Information (PDF)

pp. 246