CSDL - Proceedings I

Message from the Program Chair (PDF)

pp. ix

Organizing Committee (PDF)

pp. x

List of Reviewers (PDF)

pp. xi

Session 1: Invited Address

Design Methods for Multiple-Valued Input Address Generators (Abstract)

Tsutomu Sasao, Kyushu Institute of Technology, Japan

pp. 1

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Session 2: Circuits I

Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic (Abstract)

Naofumi Homma, Tohoku University, Sendai, Japan

Takafumi Aoki, Tohoku University, Sendai, Japan

Tatsuo Higuchi, Tohoku Institute of Technology, Japan

pp. 2

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On Designs of Radix Converters Using Arithmetic Decompositions (Abstract)

Yukihiro Iguchi, Meiji University, Kawasaki 214-8571, Japan

Tsutomu Sasao, Kyushu Institute of Technology, Iizuka , Japan

Munehiro Matsuura, Kyushu Institute of Technology, Iizuka , Japan

pp. 3

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New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit Design (Abstract)

Eun-Ju Choi, Chungbuk Nat?l University

Kyoung-Rok Cho, Chungbuk Nat?l University

Je-Hoon Lee, USC

pp. 4

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Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic (Abstract)

Akira Mochizuki, Tohoku University, Japan

Takahiro Hanyu, Tohoku University, Japan

pp. 5

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Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture (Abstract)

Haque Mohammad Munirul, Tohoku University, Japan

Tomoaki Hasegawa, Tohoku University, Japan

Michitaka Kameyama, Tohoku University, Japan

pp. 6

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Session 3: Algebra and Logic

On the Ranges of Algebraic Functions in Lattices - A Preliminary Report (Abstract)

Sergiu Rudeanu, University of Bucharest, Romania

Dan A. Simovici, Univ. of Massachusetts, Boston

pp. 7

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Upper and Lower Bounds on the Number of Disjunctive Forms (Abstract)

Hisayuki TATSUMI, Tsukuba University of Technology, Japan

Masahiro MIYAKAWA, Tsukuba University of Technology, Japan

Masao MUKAIDONO, Meiji University, Japan

pp. 8

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Completeness of a Hypersequent Calculus for Some First-order Godel Logics with Delta (Abstract)

Matthias Baaz, Technische Universitat Wien, Vienna, Austria

Norbert Preining, Universit`a di Siena, Italy

Richard Zach, University of Calgary

pp. 9

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Assumption based multi-valued semantics for extended logic programs (Abstract)

Daniel Stamate, University of London, UK

pp. 10

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Session 4: Circuits II

Implementation of Multiple-Valued CAM Functions by LUT Cascades (Abstract)

Tsutomu Sasao, Kyushu Institute of Technology, Japan

Jon T. Butler, Naval Postgraduate School, Monterey, CA.

pp. 11

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The new architecture of radix-4 Chinese abacus adder (Abstract)

Shu-Chung Yi, National Changhua University of Education, Changhua, Taiwan

Kun-Tse Lee, National Changhua University of Education, Changhua, Taiwan

Jin-Jia Chen, National Changhua University of Education, Changhua, Taiwan

Chien-Hung Lin, National Changhua University of Education, Changhua, Taiwan

Chuen-Ching Wang, National Changhua University of Education, Changhua, Taiwan

Chin-Fa Hsieh, China Institute of Technology, Taipei, Taiwan

Chih-Yung Lu, China Institute of Technology, Taipei, Taiwan

pp. 12

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Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit (Abstract)

Haque Mohammad Munirul, Tohoku University, Japan

Michitaka Kameyama, Tohoku University, Japan

pp. 13

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Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits (Abstract)

Akira Mochizuki, Tohoku University, Japan

Takeshi Kitamura, Tohoku University, Japan

Hirokatsu Shirahama, Tohoku University, Japan

Takahiro Hanyu, Tohoku University, Japan

pp. 14

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A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors (Abstract)

los Roberto Junior Mingoto, University of Campinas, Brasil

pp. 15

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Session 5: Invited Address

Signal Processing Algorithms and Multiple-Valued Logic Design Methods (Abstract)

Jaakko Astola, Tampere University of Technology, Finland

Radomir S. Stankovic, Dept. of Computer Science, Faculty of Electronics, 18000 Nis, Serbia

pp. 16

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Session 6: Circuits III

Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals (Abstract)

Yoshihiro NAKATANI, Graduate School of Information Sciences, Tohoku Univers, Japan

Masanori HARIYAMA, Graduate School of Information Sciences, Tohoku Univers, Japan

Michitaka KAMEYAMA, Graduate School of Information Sciences, Tohoku Univers, Japan

pp. 17

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A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices (Abstract)

Henning Gundersen, University of Oslo, Norway

Yngvar Berg, University of Oslo, Norway

pp. 18

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A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors (Abstract)

Katsuhiko Degawa, Tohoku University, Sendai 980-8579, Japan

Takafumi Aoki, Tohoku University, Sendai 980-8579, Japan

Tatsuo Higuchi, Tohoku Institute of Technology, Japan

Hiroshi Inokawa, NTT Corporation, Japan

Katsuhiko Nishiguchi, NTT Corporation, Japan

Yasuo Takahashi, Graduate School of Information Science and Technology, Hokkaido University, Japan

pp. 19

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A Feedback-Signal Shaping Technique for Multi-Level Continuous-Time Delta-Sigma Modulators with Clock-Jitter (Abstract)

Mitsuhiro Tanihata, Sophia University, Japan

Takao Waho, Sophia University, Japan

pp. 20

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Session 7: Algebra and Clones

Commuting Hyperoperations (Abstract)

Jovanka Pantovic, University of Novi Sad, Serbia and Montenegro

Gradimir Vojvodic, University of Novi Sad, Serbia and Montenegro

pp. 21

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Theoretical Basis of Commutation Theory for Partial Clones (Abstract)

Lucien Haddad, Lucien Haddad

Hajime Machida, Hajime Machida

Ivo G. Rosenberg, Ivo G. Rosenberg

pp. 22

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Associativity Test in Hypergroupoids (Abstract)

Masahiro Miyakawa, Tsukuba University of Technology, Japan

Ivo G. Rosenberg, Universite de Montreal, Canada

Hisayuki Tatsumi, Tsukuba Unversity of Technology, Japan

pp. 23

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Some Observations on Minimal Clones (Abstract)

Hajime Machida, Hajime Machida

Michael Pinsker, Michael Pinsker

pp. 24

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Session 8: Systems and Satisfiability

Efficiency of Multi-Valued Encoding in SAT-based ATPG (Abstract)

Goerschwin Fey, University of Bremen, Germany

Junhao Shi, University of Bremen, Germany

Rolf Drechsler, University of Bremen, Germany

pp. 25

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Towards Solving Many-Valued MaxSAT (Abstract)

Josep Argelich, Universitat de Lleida, Spain

Xavier Domingo, GPS MicroSAT, Spain

Chu-Min Li, Universite de Picardie, France

Felip Manya, IIIA-CSIC, Spain

Jordi Planes, Universitat de Lleida, Spain

pp. 26

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Random Multiple-Valued Networks: Theory and Applications (Abstract)

Elena Dubrova, Royal Institute of Technology, IMIT/KTH, Sweden

pp. 27

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Session 9: Decision Diagrams and Decision Trees

Representations of Elementary Functions Using Binary Moment Diagrams (Abstract)

Tsutomu Sasao, Kyushu Institute of Technology, Japan

Shinobu Nagayama, Hiroshima City University, Japan

pp. 28

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Embedding and Assembling Techniques for Spatial Computing Structure Design using Decision Trees and Diagrams (Abstract)

S. N. Yanushkevich, University of Calgary, Canada

V. P. Shmerko, University of Calgary, Canada

O. R. Boulanov, University of Calgary, Canada

pp. 29

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QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits (Abstract)

D. Michael Miller, University of Victoria, Victoria, BC, Canada

Mitchell A. Thornton, Southern Methodist University, Dallas, TX, USA

pp. 30

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Arithmetic-Haar Spectral Transform Decision Diagrams (Abstract)

Bogdan J. Falkowski, Nanyang Technological University, Singapore

Shixing Yan, Nanyang Technological, Singapore

pp. 31

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Session 10: Quantum Logic and Spectral Techniques

Multi-Valued Quantum Logic (Abstract)

Michael Katz, Haifa University, Mount Carmel, Haifa, Israel

pp. 32

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A Quantum CAD Accelerator Based on Grover?s Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form (Abstract)

Lun Li, Southern Methodist University, Dallas, TX

Mitch Thornton, Southern Methodist University, Dallas, TX

Marek Perkowski, Portland State University, Portland, OR

pp. 33

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Generation and Relation of Quaternary and Binary Linearly Independent Transforms (Abstract)

Bogdan J. Falkowski, Nanyang Technological University, Singapore

Cheng Fu, Nanyang Technological University, Singapore

pp. 34

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Properties of matrix-valued spectral coefficients obtained with the Fourier Transform on a non-Abelian group (Abstract)

Claudio Moraga, European Center of Soft Computing de Barredo Building of Sc. and Tech., Spain

Radomir Stankovic, Dept. Computer Science Faculty of Electronics, Serbia

Jaakko Astola, Tampere University of Technology, Finland

pp. 35

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Author Index

Author Index (PDF)

pp. 36