Message from the Symposium Chairs

List of reviewers (PDF)

pp. xii

Message from the Program Chair (PDF)

pp. x

Organizing Committee (PDF)

pp. xi-xi

Two New Awards (PDF)

pp. xiii

Session 1: Keynote Address

Classical vs Quantum Fingerprinting (Abstract)

Barry Sanders, University of Calgary, Canada

pp. 2-5

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Session 2A: Algebra I

An Abstract Axiomatization of the Notion of Entropy (Abstract)

Ivo G. Rosenberg, Universit? de Montr?al, Canada

Dan A. Simovici, Univ. of Massachusetts Boston, USA

pp. 8-13

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On Prior's Three-Valued Modal Logic Q (Abstract)

Seiki Akama, Teikyo Heisei University, Japan

Yasunori Nagata, University of the Ryukyus, Japan

pp. 14-19

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Polynomial Ring Calculus for Many-Valued Logics (Abstract)

Walter Carnielli, State University of Campinas - UNICAMP, Brazil

pp. 20-25

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Partially Ordered Set with Residuated t-norm (Abstract)

Michiro Kondo, Tokyo Denki University, Japan

Mayuka F. Kawaguchi, Hokkaido University, Japan

pp. 26-29

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Session 2B: Circuits I

A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors (Abstract)

Katsuhiko Degawa, Tohoku University, Japan

Takafumi Aoki, Tohoku University, Japan

Hiroshi Inokawa, NTT Corporation, Japan

Tatsuo Higuchi, Tohoku Institute of Technology, Japan

Yasuo Takahashi, Hokkaido University, Japan

pp. 32-38

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Multi-Valued DNA-Based Electronic Nanodevices (Abstract)

Marina Alexandra Lyshevski, Microsystems and Nanotechnologies, Webster, NY

pp. 39-42

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A Design of 10-GHz Delta-Sigma Modulator using a 4-Level Differential Resonant-Tunneling Quantizer (Abstract)

Keisuke Eguchi, Sophia University, Japan

Masaru Chibashi, Sophia University, Japan

Takao Waho, Sophia University, Japan

pp. 43-47

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Multi-Valued Nanoelectronics With Fullerenes (Abstract)

Sergey Edward Lyshevski, Rochester Institute of Technology, New York

pp. 48-53

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A Novel Ternary Switching Element Using CMOS Recharge Semi Floating-Gate Devices (Abstract)

Henning Gundersen, University of Oslo, Norway

Ren? Jensen, University of Oslo, Norway

Yngvar Berg, University of Oslo, Norway

pp. 54-58

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Session 3: Tutorial on Clones

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Session 4A: Logic Design I

Test Generation and Fault Localization for Quantum Circuits (Abstract)

Marek Perkowski, Portland State University, Portland, OR

Jacob Biamonte, Portland State University, Portland, OR

Martin Lukac, Portland State University, Portland, OR

pp. 62-68

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Complete Bi-Decomposition of Multiple-Valued Functions Using MIN and MAX Gates (Abstract)

Bernd Steinbach, TU Bergakademie Freiberg

Christian Lang, IMMS gGmbH Erfurt

pp. 69-74

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Hardware to Compute Walsh Coefficients (Abstract)

Yukihiro Iguchi, Meiji University

Tsutomu Sasao, Kyushu Institute of Technology

pp. 75-81

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Three Dimensional Multi-Valued Design in Nanoscale Integrated Circuits (Abstract)

Sergey Edward Lyshevski, Rochester Institute of Technology, New York

pp. 82-87

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Multiple-Valued Logic Approach for a Systolic^2 AB Circuit in Galois Field (Abstract)

Nabil Abu-Khader, Wayne State University, Detroit, MI

Pepe Siy, Wayne State University, Detroit, MI

pp. 88-93

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Session 4B: Clones and Algebraic Aspects

On the Partial Hyperclone Lattice (Abstract)

Jovanka Pantovic, University of Novi Sad, Serbia and Montenegro

Gradimir Vojvodic, University of Novi Sad, Serbia and Montenegro

pp. 96-100

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Partial Clones Determined by Concatenated Relations (Abstract)

L. Haddad, Coll?ge militaire royal du Canada, Canada

I. G. Rosenberg, Universit? de Montr?al, Canada

pp. 101-106

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Semirigid Equivalence Relations - A New Proof Method (Abstract)

Masahiro Miyakawa, Tsukuba College of Technology, Japan

Ivo G. Rosenberg, Universit? de Montr?al, Canada

Hisayuki Tatsumi, Tsukuba College of Technology, Japan

pp. 107-112

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Session 5A: Circuits II

Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer (Abstract)

Tomoaki Hasegawa, Tohoku University, Japan

Yuya Homma, Tohoku University, Japan

Michitaka Kameyama, Tohoku University, Japan

pp. 114-119

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Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic (Abstract)

Haque Mohammad Munirul, Tohoku University, Japan

Tomoaki Hasegawa, Tohoku University, Japan

Michitaka Kameyama, Tohoku University, Japan

pp. 120-125

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Multiple-Valued Caches for Power-Efficient Embedded Systems (Abstract)

Emre ?zer, ARM Ltd. Cambridge, UK

Resit Sendag, University of Rhode Island, USA

David Gregg, Trinity College Dublin, Ireland

pp. 126-131

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Analog Soft Decoding for Multi-Level Memories (Abstract)

Chris Winstead, Utah State University, Logan, UT

pp. 132-137

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Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders (Abstract)

Naoya Onizawa, Tohoku University, Japan

Akira Mochizuki, Tohoku University, Japan

Takahiro Hanyu, Tohoku University, Japan

Vincent C. Gaudet, University of Alberta, Edmonton, Canada

pp. 138-143

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Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation (Abstract)

Hideki Fukuda, New Japan Radio Co., Ltd.

pp. 144-151

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Session 5B: Fuzzy Logic and Neural Networks

The Alleged Limitations of Fuzzy Control (Abstract)

Phil Serchuk, University of Calgary, Canada

pp. 154-159

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A New Aspect for the Optimization of Fuzzy If-Then Rules (Abstract)

Claudio Moraga, University of Dortmund, Germany

Rodrigo Salas, University of Valpara?so, Chile

pp. 160-165

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Session 6: Invited Address

Approaching the Physical Limits of Computing (Abstract)

Michael P. Frank, FAMU-FSU College of Engineering

pp. 168-185

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Session 7A: Spectral Transforms

Remarks on the Structure of Matrix-Valued Spectral Transforms on Finite Non-Abelian Groups (Abstract)

Radomir S. Stankovic, Faculty of Electronics, Serbia

Claudio Moraga, Dortmund University, Germany

Jaakko Astola, Tampere University of Technology, Finland

pp. 188-193

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The Karhunen-Lo?ve Transform of Discrete MVL Functions (Abstract)

Mitchell Aaron Thornton, Southern Methodist University, Dallas, Texas

pp. 194-199

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Properties and Relations of Quaternary Linearly Independent Helix Transformations (Abstract)

Cheng Fu, Nanyang Technological University, Singapore

Bogdan J. Falkowski, Nanyang Technological University, Singapore

pp. 200-205

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Classes of Fastest Quaternary Linearly Independent Transformations (Abstract)

Bogdan J. Falkowski, Nanyang Technological University, Singapore

Cheng Fu, Nanyang Technological University, Singapore

pp. 206-211

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Session 7B: Algebra II

Many-Valued Intuitionistic Implication and Inference Closure in a Bilattice-Based Logic (Abstract)

Zoran Majkic, UMIACS, University of Maryland, College Park, MD

pp. 214-220

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A Note on Triangulation of PostAlgebras and ?Leibnizian? Lattices (Abstract)

Michel Serfati, Universit? Paris VII-Denis Diderot, France

pp. 221-226

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Centralizers of Monoids Containing the Symmetric Group (Abstract)

Hajime Machida, Hitotsubashi University, Japan

Ivo G. Rosenberg, Universit? de Montr?al, Canada

pp. 227-233

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Session 8: Invited Address

Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem (Abstract)

Marek Perkowski, Portland State University, Oregon; Korea Advanced Institute of Science and Technology, KAIST, Daejeon, Republic of Korea

Tsutomu Sasao, Kyushu Institute of Technology, Japan

Jong-Hwan Kim, Korea Advanced Institute of Science and Technology, KAIST, Daejeon, Republic of Korea

Martin Lukac, Portland State University, Oregon

Jeff Allen, Portland State University, Oregon

Stefan Gebauer, Chemnitz University of Technology, Germany

pp. 236-248

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Session 9A: Logic Design II

Controlling the Memory During Manipulation of Word-Level Decision Diagrams (Abstract)

Sebastian Kinder, University of Bremen, Germany

G?rschwin Fey, University of Bremen, Germany

Rolf Drechsler, University of Bremen, Germany

pp. 250-255

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Radix Converters: Complexity and Implementation by LUT Cascades (Abstract)

Tsutomu Sasao, Kyushu Institute of Technology, Japan

pp. 256-263

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Dynamic Reliability Indices for k-out-of-n Multi-State System (Abstract)

E. Zaitseva, University of Zilina, Slovakia

V. Levashenko, University of Zilina, Slovakia

K. Matiasko, University of Zilina, Slovakia

S. Puuronen, University of Jyv?skyl?, Finland

pp. 264-269

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A Characterization of Antisymmetry in Boolean and Multi-Valued Functions (Abstract)

J. E. Rice, University of Lethbridge, Alberta, Canada

J. C. Muzio, University of Victoria, British Columbia, Canada

pp. 270-275

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Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation Technique (Abstract)

Daniel H. Y. Teng, University of Saskatchewan, Saskatoon, SK, Canada

Ronald J. Bolton, University of Saskatchewan, Saskatoon, SK, Canada

pp. 276-281

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Session 9B: Algebra III

Normal Forms for the One-Variable Fragment of H?jek's Basic Logic (Abstract)

Stefano Aguzzoli, University of Milano, Italy

Brunella Gerla, University of Salerno, Italy

pp. 284-289

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Mapping Many-Valued CNF Formulas to Boolean CNF Formulas (Abstract)

C. Ans?tegui, Cornell University, Ithaca, NY

F. Many?, IIIA-CSIC, Bellaterra, Spain

pp. 290-295

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Quantification in Non-Deterministic Multi-Valued Structures (Abstract)

Arnon Avron, Tel-Aviv University

Anna Zamansky, Tel-Aviv University

pp. 296-301

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Author Index (PDF)

pp. 302-302