CSDL - Proceedings I

Message from the Program Chair (PDF)

pp. xii

Symposium Committee (PDF)

pp. xiii

Referees (PDF)

pp. xiv

Session 1 Keynote Address

Hard vs. Soft: The Central Question of Pre-Fabricated Silicon (Abstract)

Jonathan Rose, University of Toronto

pp. 2-5

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Session 2A Emerging Technologies

Multiple-Input Resonant-Tunneling Logic Gates for Flash A/D Converter Applications (Abstract)

Yuki Tsuji, Sophia University

Takao Waho, Sophia University

pp. 8-13

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A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs (Abstract)

Arijit Raychowdhury, Purdue University

Kaushik Roy, Purdue University

pp. 14-19

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Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication (Abstract)

Tomohiro Takahashi, Tohoku University

Takahiro Hanyu, Tohoku University

pp. 20-25

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Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic (Abstract)

Haque Mohammad Munirul, Tohoku University

Michitaka Kameyama, Tohoku University

pp. 26-30

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Session 2B Logic

Resolution-Based Decision Procedures for the Positive Theory of Some Finitely Generated Varieties of Algebras (Abstract)

Viorica Sofronie-Stokkermans, Max-Planck-Institut für Informatik

pp. 32-37

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Uniform Description of Calculi for All t-Norm Logics (Abstract)

Stefano Aguzzoli, University of Milano

pp. 38-43

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Weakly Associative Functions on [0, 1] as Logical Connectives (Abstract)

Mayuka F. Kawaguchi, Hokkaido University

Masaaki Miyakoshi, Hokkaido University

pp. 44-48

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Automata over MV-Algebras (Abstract)

Brunella Gerla, University of Salerno

pp. 49-54

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Session 3 Invited Address

Quantum Communication Complexity: A Survey (PDF)

Gilles Brassard, Université de Montréal

pp. 56

Session 4A Reversible Logic

Ternary Galois Field Expansions for Reversible Logic and Kronecker Decision Diagrams for Ternary GFSOP Minimization (Abstract)

Mozammel H. A. Khan, East West University

Marek A. Perkowski, Portland State University

Mujibur R. Khan, East West University

pp. 58-67

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On Universality of General Reversible Multiple-Valued Logic Gates (Abstract)

Pawel Kerntopf, Warsaw University of Technology

Marek A. Perkowski, Portland State University

Mozammel H. A. Khan, East West University

pp. 68-73

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A Synthesis Method for MVL Reversible Logic (Abstract)

D. Michael Miller, University of Victoria

Gerhard W. Dueck, University of New Brunswick

Dmitri Maslov, University of Victoria

pp. 74-80

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Reversible Fast Permutation Transforms for Quantum Circuit Synthesis (Abstract)

Anas N. Al-Rabadi

pp. 81-86

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Quantum Circuit Synthesis Using Classes of GF(3) Reversible Fast Spectral Transforms (Abstract)

Anas N. Al-Rabadi

pp. 87-93

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Session 4B Clones

On Partial Clones containing Maximal Clones (Abstract)

Lucien Haddad, Collège Militaire Royal du Canada

Dietlinde Lau, Universität Rostock

pp. 96-101

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Monoids whose Centralizer is the Least Clone (Abstract)

Hajime Machida, Hitotsubashi University

Ivo G. Rosenberg, Université de Montréal

pp. 102-108

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Algebraic Properties of Totally Irreducible Elements of Clone Lattices (Abstract)

Grant R. Pogosyan, International Christian University

Ivo G. Rosenberg, Université deMontréal

pp. 109-114

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Minimal Partial Hyperclones on a Two-Element Set (Abstract)

Jovanka Pantović, University of Novi Sad

Gradimir Vojvodić, University of Novi Sad

pp. 115-119

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Some Properties of Local Partial Clones on an Infinite Set (Abstract)

B. A. Romov, Bayard Rustin High School for the Humanities

pp. 120-125

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Session 5A Circuits I

Signed Digit CMOS (SD-CMOS) Logic Circuits with Static Operation (Abstract)

Hideki Fukuda, New Japan Radio Co., Ltd.

pp. 128-134

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A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC (Abstract)

Omid Mirmotahari, University of Oslo

Yngvar Berg, University of Oslo

pp. 135-138

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Sesion 5B Fuzzy Logic and Learning

Optimizing the Defuzzifier Timing for the Fuzzy Control of a Servodrive (Abstract)

Dan Mihai, University of Craiova

pp. 142-147

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A Metasemantics to Refine Fuzzy If-Then Rules (Abstract)

Claudio Moraga, University of Dortmund

pp. 148-153

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Evolutionary Strategy for Learning Multiple-Valued Logic Functions (Abstract)

Alioune Ngom, University of Windsor

Dan A. Simovici, University of Massachusetts at Boston

Ivan Stojmenović, University of Ottawa

pp. 154-160

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Session 6A Reed Muller Expansions

Fast Optimization of Fixed-Polarity Reed-Muller Expansions over GF(5) (Abstract)

Bogdan J. Falkowski, Nanyang Technological University

Cicilia C. Lozano, Nanyang Technological University

Susanto Rahardja, Institute for Infocomm Research

pp. 162-167

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On the Optimisation of Reed-Muller Expressions (Abstract)

K. J. Adams, University of Ulster

J. McGregor, University of Ulster

pp. 168-176

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Spectra Generation for Fixed-Polarity Reed-Muller Transform over GF(5) (Abstract)

Bogdan J. Falkowski, Nanyang Technological University

Cicilia C. Lozano, Nanyang Technological University

Susanto Rahardja, Institute for Infocomm Research

pp. 177-183

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Derivatives for Multiple-Valued Functions Induced by Galois Field and Reed-Muller-Fourier Expressions (Abstract)

Radomir S. Stanković

Claudio Moraga, Dortmund University

Jaakko Astola, Tampere University of Technology

pp. 184-189

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Session 6B Circuits II

Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding (Abstract)

Akira Mochizuki, Tohoku University

Takashi Takeuchi, Tohoku University

Takahiro Hanyu, Tohoku University

pp. 192-197

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Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit (Abstract)

Soo Jin Park, INHA University

Byoung Hee Yoon, INHA University

Kwang Sub Yoon, INHA University

Heung Soo Kim, INHA University

pp. 198-203

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A Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Technique and its Applications (Abstract)

Daniel H. Y. Teng, University of Saskatchewan

Ronald J. Bolton, University of Saskatchewan

pp. 204-209

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A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic (Abstract)

Omid Mirmotahari, University of Oslo

Yngvar Berg, University of Oslo

pp. 210-213

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Session 7 Round Table Discussion

Multiple-Valued Logic: Challenges and Opportunities

Session 8A MDDs

On the Minimization of Average Path Lengths for Heterogeneous MDDs (Abstract)

Shinobu Nagayama, Kyushu Institute of Technology

Tsutomu Sasao, Kyushu Institute of Technology

pp. 216-222

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Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Properties (Abstract)

Dragan Janković

Radomir S. Stanković

Rolf Drechsler, University of Bremen

pp. 223-228

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Edge-Valued Decision Diagrams for Multiple-Valued Functions (Abstract)

Radomir S. Stanković

Jaakko Astola, Tampere University of Technology

pp. 229-234

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Algorithms for Taylor Expansion Diagrams (Abstract)

Goerschwin Fey, University of Bremen

Rolf Drechsler, University of Bremen

Maciej Ciesielski, University of Massachusetts at Amherst

pp. 235-240

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Session 8B Mathematical Aspects

Polynomial Functions on a Central Relation (Abstract)

Dietmar Schweigert, University of Kaiserslautern

pp. 242-244

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A Graph-Theoretical Approach to Boolean Interpolation of Non-Boolean Functions (Abstract)

Sergiu Rudeanu, University of Bucharest

Dan A. Simovici, University of Massachusetts at Boston

pp. 245-250

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The Interface between P and NP in Signed CNF Formulas (Abstract)

C. Ansótegui, Universitat de Lleida

R. Béjar, Universitat de Lleida

A. Cabiscol, Universitat de Lleida

F. Manyà, Universitat de Lleida

pp. 251-256

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Characterization Theorem of Lattice Implication Algebras (Abstract)

Michiro Kondo, Tokyo Denki University

pp. 257-260

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A Single-Electron-Transistor Logic Gate Family and Its Application — Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic (Abstract)

Session 9A Single Electron Logic

Katsuhiko Degawa, Tohoku University

Takafumi Aoki, Tohoku University

Tatsuo Higuchi, Tohoku Institute of Technology

Hiroshi Inokawa, NTT Corporation

Yasuo Takahashi, NTT Corporation

pp. 262-268

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A Single-Electron-Transistor Logic Gate Family and Its Application — Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions (Abstract)

Hiroshi Inokawa, NTT Corporation

Yasuo Takahashi, NTT Corporation

Katsuhiko Degawa, Tohoku University

Takafumi Aoki, Tohoku University

Tatsuo Higuchi, Tohoku Institute of Technology

pp. 269-274

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Three Dimensional Multiple Valued Circuits Design Based on Single-Electron Logic (Abstract)

S. N. Yanushkevich, University of Calgary

V. P. Shmerko, University of Calgary

L. Guy, University of Calgary

D. C. Lu, University of Calgary

pp. 275-280

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Session 9B Probability & Uncertainty

Non-Deterministic Matrices (Abstract)

Arnon Avron, Tel-Aviv University

Iddo Lev, Stanford University

pp. 282-287

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Controlling Uncertainty in Discretization of Continuous Data (Abstract)

Denis V Popel, Baker University

Elena I Popel, Kansas University

pp. 288-293

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Many Valued Probability Theory (Abstract)

Charles G. Morgan, University of Victoria

pp. 294-299

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Session 10A Digital Design

A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades (Abstract)

Yukihiro Iguchi, Meiji University

Tsutomu Sasao, Kyushu Institute of Technology

Munehiro Matsuura, Kyushu Institute of Technology

pp. 302-308

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A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued Functions (Abstract)

Elena Dubrova, Royal Institute of Technology

pp. 309-314

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Iterative-Based Minimization of Unary 4-Valued Functions for Current-Mode CMOS Realization (Abstract)

Mostafa Abd-El-Barr, King Fahd University of Petroleum & Minerals

Louai Al-Awami, King Fahd University of Petroleum & Minerals

pp. 315-320

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On the Minimization of Multiple-Valued Input Binary-Valued Output Functions (Abstract)

Hafiz Md. Hasan Babu, University of Dhaka

Moinul Islam Zaber, University of Dhaka

Md.Rafiqul Islam, University of Dhaka

Md. Mazder Rahman, University of Dhaka

pp. 321-326

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Session 10B Circuits III

Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications (Abstract)

Haque Mohammad Munirul, Tohoku University

Michitaka Kameyama, Tohoku University

pp. 328-333

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Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH (Abstract)

Kazuya Ishida, Tohoku University

Naofumi Homma, Tohoku University

Takafumi Aoki, Tohoku University

Tatsuo Higuchi, Tohoku Institute of Technology

pp. 334-339

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A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices (Abstract)

Hiromitsu Kimura, Tohoku University

Kostas Pagiamtzis, University of Toronto

Ali Sheikholeslami, University of Toronto

Takahiro Hanyu, Tohoku University

pp. 340-345

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Basic Multiple-Valued Functions Using Recharge CMOS Logic (Abstract)

Y. Berg, University of Oslo

S. Aunet, Norwegian University of Science and Technology

?. N?ss, University of Oslo

O. Mirmotahari, University of Oslo

pp. 346-351

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Author Index

Author Index (PDF)

pp. 352-353