Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH

Kazuya Ishida; Tatsuo Higuchi; Naofumi Homma; Takafumi Aoki

doi:10.1109/ISMVL.2004.1319964

I
ISMVL
2004
34th International Symposium on Multiple-Valued Logic (ISMVL'04)
Abstract - Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH

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34th International Symposium on Multiple-Valued Logic (ISMVL'04)

Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH

University of Toronto, Toronto, Canada

May 19-May 22

ISBN: 0-7695-2130-4

	ASCII Text	x
	Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi, "Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH," 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, pp. 334-339, 34th International Symposium on Multiple-Valued Logic (ISMVL'04), 2004.

	BibTex	x
	@article{ 10.1109/ISMVL.2004.1319964, author = {Kazuya Ishida and Naofumi Homma and Takafumi Aoki and Tatsuo Higuchi}, title = {Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH}, journal ={2013 IEEE 43rd International Symposium on Multiple-Valued Logic}, volume = {0}, year = {2004}, issn = {0195-623X}, pages = {334-339}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISMVL.2004.1319964}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic TI - Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH SN - 0195-623X SP334 EP339 A1 - Kazuya Ishida, A1 - Naofumi Homma, A1 - Takafumi Aoki, A1 - Tatsuo Higuchi, PY - 2004 KW - null VL - 0 JA - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic ER -

Kazuya Ishida, Tohoku University

Naofumi Homma, Tohoku University

Takafumi Aoki, Tohoku University

Tatsuo Higuchi, Tohoku Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISMVL.2004.1319964

This paper proposes the basic concept of arithmetic description language called ARITH. The use of ARITH makes possible (i) formal description of arithmetic algorithms including those using unconventional number systems, (ii) formal verification of described arithmetic algorithms, and (iii) translation of arithmetic algorithms to equivalent HDL codes. In this paper, we demonstrate the potential of ARITH through an experimental design of parallel multipliers using binary signed-digit number system.

Citation:

Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi, "Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH," ismvl, pp.334-339, 34th International Symposium on Multiple-Valued Logic (ISMVL'04), 2004

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