CSDL - Proceedings I

Message from the Program Committee (PDF)

pp. x

Reviewers (PDF)

pp. xi

Invited Talk

Equations in the Algebra of Logic (Abstract)

Sergiu Rudeanu, University of Bucharest

pp. 2

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Algebra I

Some Results on the Centralizers of Monoids in Clone Theory (Abstract)

Hajime Machida, Hitotsubashi University

Masahiro Miyakawa, Tsukuba College of Technology

Ivo G. Rosenberg, Université de Montréal

pp. 10

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Partial Hyperclones on a Finite Set (Abstract)

B.A. Romov, Bayard Rustin High School for the Humanities

pp. 17

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On the Structures of Weak Interlaced Bilattice (Abstract)

Michiro Kondo, Shimane University

pp. 23

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Logical Design I

Improving the Characterization of p-Valued Threshold Functions (Abstract)

Claudio Moraga, Technical University of Madrid, University of Dortmund

pp. 28

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A Conjunctive Canonical Expansion of Multiple-Valued Functions (Abstract)

Elena Dubrova, Royal Institute of Technology

Petra Färm, Royal Institute of Technology

pp. 35

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Sierpinski Gaskets for Logic Functions Representation (Abstract)

Denis V. Popel, Baker University

Anita Dani, University of Wollongong

pp. 39

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Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and Literals (Abstract)

Noboru Tkagi, Toyama Prefectural University

Kyoichi Nakashima, Toyama Prefectural University

pp. 46

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Circuits I

Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI (Abstract)

Yasushi Yuminaka, Gunma University

Tatsuya Morishita, Gunma University

Takafumi Aoki, Gunma University

Tatsuo Higuchi, Gunma University

pp. 54

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An Impact of Introducing Multi-Level Signals to a Bandpass Cascaded Delta-Sigma Modulator (Abstract)

Takao Waho, Sophia University

Shin-ya Kobayashi, Sophia University

Koji Matsuura, Sophia University

pp. 61

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Voltage Comparator Circuits for Multiple-Valued CMOS Logic (Abstract)

Yongjian Brandon Guo, University of California, Davis

K. Wayne Current, University of California, Davis

pp. 67

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Logical Design II

Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multiple-Valued Logic Functions (Abstract)

Dragan Jankovic, University of Niš

Radomir S. Stankovic, University of Niš

pp. 76

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Comparison of Different Features of Quaternary Reed-Muller Canonical Forms and Some New Statistical Results (Abstract)

K. J. Adams, Magee College

J. McGregor, Magee College

pp. 83

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Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection (Abstract)

Boris Polianskikh, McGill University

Zeljko Zilic, McGill University

pp. 89

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Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis (Abstract)

Masanori Natsui, Tohoku University

Takafumi Aoki, Tohoku University

Tatsuo Higuchi, Tohoku University

pp. 96

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Consequence and Complexity in Infinite-Valued Logic: A Survey (Abstract)

Vincenzo Marra, University of Milan

Daniele Mundici, University of Milan

pp. 104

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Some Remarks on Linear Transform of Variables in Representation of Adders by Word-Level Expressions and Spectral Transform Decision Diagrams (Abstract)

Spectral Techniques

Radomir S. Stankovic, Faculty of Electronics?

Jaakko T. Astola?, Tampere University of Technology?

pp. 116

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Chrestenson Spectrum Computation Using Cayley Color Graphs (Abstract)

Mitchell A. Thornton, Mississippi State University

D. Michael Miller, University of Victoria

Whitney J. Townsend, Mississippi State University

pp. 123

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The Role of Super-Fast Transforms in Speeding Up Quantum Computations (Abstract)

Zeljko Zilic, McGill University

Katarzyna Radecka, McGill University

pp. 129

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Multiple-Valued and Spectral Approach to Lossless Compression of Binary, Gray Scale and Color Biomedical Images (Abstract)

Bogdan J. Falkowski, Nanyang Technological University

Beata T. Olejnicka, Nanyang Technological University

pp. 136

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Circuits II

Design of Dynamic Reliability Indices (Abstract)

Elena N. Zaitseva, Belarus State Economic University

Vitaly G. Levashenko, Belarus State Economic University, University of Zilina

pp. 144

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PODEM Based on Static Testability Measures and Dynamic Testability Measures for Multiple-Valued Logic Circuits (Abstract)

Naotake Kamiura, Himeji Institute of Technology

Teijiro Isokawa, Himeji Institute of Technology

Nobuyuki Matsui, Himeji Institute of Technology

pp. 149

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Design of Ternary Schmitt Triggers Based on Its Sequential Characteristics (Abstract)

Yinshui Xia, Napier Universit

Xunwei Wu, Ningbo University

Penjung Wang, Ningbo University

pp. 156

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Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition (Abstract)

Hiromitsu Kimura, Tohoku University

Takahiro Hanyu, Tohoku University

Michitaka Kameyama, Tohoku University

pp. 161

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Optimization of Multi-Valued Multi-Level Networks (Abstract)

R. Brayton, University of California, Berkeley

M. Gao, University of California, Berkeley

J-H. Jiang, University of California, Berkeley

Y. Jiang, University of California, Berkeley

Y. Li, University of California, Berkeley

A. Mishchenko, Portland State University

S. Sinha, Parades

T. Villa, Parades

pp. 168

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Algebra II

de Morgan Bisemilattice of Fuzzy Truth Value (Abstract)

Hiroaki Kikuchi, Tokai University

Noboru Takagi, Toyama Prefectural University

pp. 180

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Independence of Each Axiom in a Set of Axioms and Complete Sets of Axioms of Boolean Algebra (Abstract)

Tomoko Ninomiya, Tamagawa University

Masao Mukaidono, Meiji University

pp. 185

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On Functions Defined on Free Boolean Algebras (Abstract)

Ivo Rosenberg, University of Montreal

Dan A. Simovici, University of Massachusetts at Boston

Szymon Jaroszewicz, University of Massachusetts at Boston

pp. 192

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Logical Design III

The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 1: LAR Based Model (Abstract)

Svetlana N. Yanushkevich, University of Calgary

Piotr Dziurzanski, Technical University of Szczecin

Vlad P. Shmerko, University of Calgary

pp. 202

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The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 2: LWL Based Model (Abstract)

Anna M. Tomaszewska, Technical University of Szczecin

Svetlana N. Yanushkevich, University of Calgary

Vlad P. Shmerko, University of Calgary

pp. 209

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Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics (Abstract)

Ilia Polian, Albert-Ludwigs-University

Piet Engelke, Albert-Ludwigs-University

Bernd Becker, Albert-Ludwigs-University

pp. 216

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Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms (Abstract)

Naofumi Takagi, Nagoya University

pp. 224

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Decision Diagrams

Variable Selection Heuristics and Optimum Decision Trees -- An Experimental Study (Abstract)

Masahiro Miyakawa, Tsukuba College of Technology

Nobuyuki Otsu, National Institute of AIST

Ivo G. Rosenberg, Université de Montréal

pp. 238

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On the Construction of Multiple-Valued Decision Diagrams (Abstract)

D. Michael Miller, University of Victoria

Rolf Drechsler, University of Bremen

pp. 245

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Evaluation of Static Variable Ordering Heuristics for MDD Construction (Abstract)

Rolf Drechsler, University of Bremen

pp. 254

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Representations of Logic Functions Using QRMDDs (Abstract)

Shinobu Nagayama, Kyushu Institute of Technology

Tsutomu Sasao, Kyushu Institute of Technology

Yukihiro Iguchi, Meiji University

Munehiro Matsuura, Kyushu Institute of Technology

pp. 261

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Circuits III

Fully Source-Coupled Logic Based Multiple-Valued VLSI (Abstract)

Tsukasa Ike, Tohoku University

Takahiro Hanyu, Tohoku University

Michitaka Kameyama, Tohoku University

pp. 270

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A Current-Mode Folding/Interpolating CMOS Analog to Quaternary Converter Using Binary to Quaternary Encoding Block (Abstract)

Sung Il Han, Inha University

Seung Yong Park, Inha University

Hyeon Kyeong Seong, Sangji University

Heung Soo Kim, Inha University

pp. 276

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Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits (Abstract)

Motoi Inaba, Tsukuba College of Technology

Koichi Tanno, Miyazaki University

Okihiko Ishizuka, Miyazaki University

pp. 282

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Author Index (PDF)

pp. 289