CSDL - Proceedings I

Message from the Co-Chairs (PDF)

pp. xiii

Reviewers (PDF)

pp. xiv

Session 1: Invited Address

Computational Neurobiology Meets Semiconductor Engineering (Abstract)

Dan Hammerstrom, Oregon Graduate Institute

pp. 3

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Session 2a: Neural and Threshold Nets

Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors (Abstract)

Jing Shen, Miyazaki University

Motoi Inaba, Miyazaki University

Koichi Tanno, Miyazaki University

Okihiko Ishizuka, Miyazaki University

pp. 15

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The Synthesis of Multiple-Valued Logic Circuits Using Local-Excitation-Type Neuron Models (Abstract)

Masayuki Matsumoto, Toyo University

Yoshinori Ueda, Toyo University

Isami Nomoto, Toyo University

pp. 21

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Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions (Abstract)

Makoto Syuto, Miyazaki University

Jing Shen, Miyazaki University

Koichi Tanno, Miyazaki University

Okihiko Ishizuka, Miyazaki University

pp. 27

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The Computing Capacity of Three-Input Multiple-Valued One-Threshold Perceptrons (Abstract)

Alioune Ngom, Lakehead University

Ivan Stojmenovic, University of Ottawa

Ratko To?ic, University of Novi Sad

pp. 33

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Session 2b: Spectral Methods

MDD-Based Synthesis of Multi-Valued Logic Networks (Abstract)

Rolf Drechsler, Albert-Ludwigs-University

Mitch Thornton, Mississippi State University

David Wessels, University of Arkansas

pp. 41

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Fast Transforms for Multiple-Valued Input Binary Output PLI Logic (Abstract)

Bogdan J. Falkowski, Nanyang Technological University

Susanto Rahardja, Nanyang Technological University

pp. 47

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Computation of Spectral Information from Logic Netlists (Abstract)

Rolf Drechsler, Albert-Ludwigs-University

Mitch Thornton, Mississippi State University

pp. 53

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Fault Analysis of the Multiple Valued Logic Using Spectral Method (Abstract)

Jong O Kim, Dongyang Technical College

Parag Lala, University of Arkansas

Young Gun Kim, Ansan College

Heung Soo Kim, Inha University

pp. 59

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Session 3: Invited Address

Neural Networks: Binary Monotonic and Multiple-Valued (Abstract)

Jacek M. Zurada, University of Louisville

pp. 67

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Session 4a: Decomposition and Data Mining

Data Mining of Weak Functional Decompositions (Abstract)

Szymon Jaroszewicz, University of Massachusetts at Boston

Dan A. Simovici, University of Massachusetts at Boston

pp. 77

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Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures (Abstract)

Artur Chojnacki, Eindhoven University of Technology

Lech Józwiack, Eindhoven University of Technology

pp. 83

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On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions (Abstract)

Tsutomu Sasao, Kyushu Institute of Technology

pp. 91

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Session 4b: Algebra I

Some Properties of Discrete Interval Truth Valued Logic (Abstract)

Noboru Takagi, Toyama Prefectural University

Kyoichi Nakashima, Toyama Prefectural University

pp. 101

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Independence of the Axioms of Boolean Algebra in Multiple-Valued Logic (Abstract)

Tomoko Ninomiya, Meiji University

Masao Mukaidono, Meiji University

pp. 107

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On Urquhart's C Logic (Abstract)

Agata Ciabattoni, Universit? Milano

pp. 113

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Session 5a: Fuzzy Logic

A New Class of Fuzzy Modifiers (Abstract)

Martine de Cock, Ghent University

Etienne E. Kerre, Ghent University

pp. 121

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Fuzzy Decision Diagrams for the Representation, Analysis and Optimization of Rule Bases (Abstract)

pp. 127

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On Algebraic Foundations of Information Granulation III Investigating the HATA-MUKAIDONO Approach (Abstract)

Helmut Thiele, University of Dortmund

pp. 133

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Session 5b: Reed-Muller Logic and Its Extensions

Experiments on FPRM Expressions for Partially Symmetric Logic Functions (Abstract)

S.N. Yanushkevich, Technical University

V.P. Shmerko, Technical University

J.T. Butler, Naval Postgraduate School

G.W. Dueck, University of New Brunswick

pp. 141

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Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams (Abstract)

Hafiz Hasan Babu, Kyushu Institute of Technology

Tsutomu Sasao, Kyushu Institute of Technology

pp. 147

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A New Algorithm to Compute Quaternary Reed-Muller Expansions (Abstract)

Susanto Rahardja, Nanyang Technological University

Bogdan J. Falkowski, Nanyang Technological University

pp. 153

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Session 6: Invited Address

Evolvable Hardware: From On-Chip Circuit Synthesis to Evolvable Space Systems (Abstract)

Adrian Stoica, California Institute of Technology

pp. 161

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Session 7a: Logic and Algebra

De Morgan Bisemilattices (Abstract)

J.A. Brzozowski, University of Waterloo

pp. 173

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Finite-Valued Approximations of Product Logic (Abstract)

Stefano Aguzzoli, ITC-IRST

Brunella Gerla, University of Milan

pp. 179

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Integration of Information in Four-Valued Logics under Non-Uniform Assumptions (Abstract)

Yann Loyer, Universite de Paris Sud

Nicolas Spyratos, Universite de Paris Sud

Daniel Stamate, Universite de Paris Sud

pp. 185

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Session 7b: Decision Diagrams

Lower Bound Sifting for MDDs (Abstract)

Dragan Jankovic, University of Nis

Wolfgang Günther, Albert-Ludwigs-University

Rolf Drechsler, Albert-Ludwigs-University

pp. 193

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Implementation of Multiple-Output Functions Using PQMDDs (Abstract)

Yukihiro Iguchi, Meiji University

Tsutomu Sasao, Kyushu Institute of Technology

Munehiro Matsuura, Kyushu Institute of Technology

pp. 199

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Fibonacci Decision Diagrams and Spectral Fibonacci Decision Diagrams (Abstract)

Radomir S. Stankovic, National Institute of Science

Milena Stankovic, National Institute of Science

Jaakko Astola, Tampere University of Technology

Karen Egiazarian, Tampere University of Technology

pp. 206

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Session 8a: Circuits I

Cost-Analysis of 4-Valued Unary Functions Implemented Using Current-Mode CMOS Circuits (Abstract)

Mostafa Abd-El-Barr, King Fahd University of Petroleum and Minerals

Abdullah Al-Mutawa, Kuwait University

pp. 215

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Implementation of Multiple-Valued Multiplier on GF(3m) Using Current Mode CMOS (Abstract)

Hyeon Kyeong Seong, Institute of Induk Technology

Jai Seok Choi, Institute of Induk Technology

Boo Sik Shin, Ansan College

Heung Soo Kim, Inha University

pp. 221

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Novel ?-Type Resistor Network in D/A Converter Based on Multiple-Valued Logic (Abstract)

Xunwei Wu, Bingbo University

Xuanchang Zhou, Zhejiang University

pp. 227

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Session 8b: Decision Diagrams and Test

Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions (Abstract)

Harald Sack, Universit?t Trier

Christoph Meinel, Universit?t Trier

Elena Dubrova, Royal Institute of Technology

pp. 233

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Dynamic Re-Encoding During MDD Minimization (Abstract)

Frank Schmiedle, Albert-Ludwigs-University

Wolfgang Günther, Albert-Ludwigs-University

Rolf Drechsler, Albert-Ludwigs-University

pp. 239

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Controllability/Observability Measures for Multiple-Valued Test Generation Based on D-Algorithm (Abstract)

Naotake Kamiura, Himeji Institute of Technology

Yutaka Hata, Himeji Institute of Technology

Nobuyuki Matsui, Himeji Institute of Technology

pp. 245

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Session 9a: Evolutionary and Information Theory Approaches

Evolutionary Multi-Level Network Synthesis in Given Design Style (Abstract)

T. Luba, Warsaw University of Technology

C. Moraga, Dortmund University,

S. Yanushkevich, Technical University

M. Opoka, Technical University

V. Shmerko, Technical University

pp. 253

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An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic Operations (Abstract)

Takahiro Hozumi, Hyogo University

Osamu Kakusho, Hyogo University

Kazuharu Yamato, Hyogo University

pp. 259

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Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4) (Abstract)

S. Yanushkevich, Technical University,

D. Popel, Technical University,

V. Shmerko, Technical University,

V. Cheushev

R. Stankovic

pp. 265

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Session 9b: Image and Language Processing

On an Architecture of Medical Image Registration System Based on Multiple-Valued Logic (Abstract)

Yutaka Hata, Himeji Institute of Technology

Syoji Kobashi, Himeji Institute of Technology

Naotake Kamiura, Himeji Institute of Technology

Yuri Kitamura, Osaka University Medical School

Toshio Yanagida, Osaka University Medical School

pp. 273

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Gray Scale Image Compression Based on Multiple-Valued Input Binary Functions, Walsh and Reed-Muller Spectra (Abstract)

Bogdan J. Falkowski, Nanyang Technological University,

Lip-San Lim, Nanyang Technological University,

pp. 279

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A Four-Valued Logic B(4) of E(9) for Modeling Human Communication (Abstract)

Raiek Alnakari, George Mason University

David Rine, George Mason University

pp. 285

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Session 10: Invited Address

Structures with Many-Valued Information and their Relational Proof Theory (Abstract)

Ivo Düntsch, University of Ulster at Jordanstown

Wendy MacCaull, St. Francis Xavier University

Ewa Orlowska, Institute of Telecommunications

pp. 293

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Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop (Abstract)

Session 11a: Circuits II

Tetsuya Uemura, NEC Corporation

Toshio Baba, NEC Corporation

pp. 305

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A Study on the Ternary Parallel Circuit Design with DCG Properties Based on the Matrix Equation (Abstract)

Gi-Noung Byun, Inha University

Chol-U Lee, Inha University

Seung-Yong Park, Inha University

Heung-Soo Kim, Inha University

pp. 311

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Novel Resonant-Tunneling Multiple-Threshold Logic Circuit Based on Switching Sequence Detection (Abstract)

Takao Waho, Sophia University

Kazufumi Hattori, Sophia University

Kouji Honda, Sophia University

pp. 317

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Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices (Abstract)

Alejandro F. Gonzalez, University of Michigan

Mayukh Bhattacharya, University of Michigan

Shriram Kulkarni, University of Michigan

Pinaki Mazumder, University of Michigan

pp. 323

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Session 11b: Theorem-Proving and Applications

The 2-SAT Problem of Regular Signed CNF Formulas (Abstract)

Bernhard Beckert, University of Karlsruhe

Reiner Hähnle, Chalmers University of Technology

Felip Manyà, University of Lleida

pp. 331

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Chaining Techniques for Automated Theorem Proving in Many-Valued Logics (Abstract)

Harald Ganzinger, Max-Planck-Institut f?r Informatik

Viorica Sofronie-Stokkermans, Max-Planck-Institut f?r Informatik

pp. 337

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High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables (Abstract)

Takafumi Aoki, Tohoku University

Kimihiko Nakazawa, Tohoku University

Tatsuo Higuchi, Tohoku University

pp. 345

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Session 12: Invited Address

Properties of Independent Components of Self-Motion Optical Flow (Abstract)

Marwan A. Jabri, Oregon Graduate Institute of Science and Technology and University of Sydney

Ki-Young Park, Korea Advanced Institute of Science and Technology

Soo-Young Lee, Korea Advanced Institute of Science and Technology

Terrence J. Sejnowski, Salk Institute

pp. 355

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Session 13: Panel Discussion

Multiple-Valued Logic: Provocative Questions

Session 14: Invited Address

A Multilevel-Cell 32Mb Flash Memory (Abstract)

M. Bauer, Intel Corporation

R. Alexis, Intel Corporation

G. Atwood, Intel Corporation

B. Baltar, Intel Corporation

A. Fazio, Intel Corporation

K. Frary, Intel Corporation

M. Hensel, Intel Corporation

M. Ishac, Intel Corporation

J. Javanifard, Intel Corporation

M. Landgraf, Intel Corporation

D. Leak, Intel Corporation

K. Loe, Intel Corporation

D. Mills, Intel Corporation

P. Ruby, Intel Corporation

R. Rozman, Intel Corporation

S. Sweha, Intel Corporation

S. Talreja, Intel Corporation

K. Wojciechowski, Intel Corporation

pp. 367

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Session 15a: Circuits III

Hardware Implementation of 'Supplementary Symmetrical Logic Circuit Structure' Concepts (Abstract)

Dan Olson, EDO llc

K. Wayne Current, K.W. Current Consulting

pp. 371

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Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch (Abstract)

K.W. Current, University of California at Davis

pp. 377

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Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels (Abstract)

Takahiro Hanyu, Tohoku University

Tsukasa Ike, Tohoku University

Michitaka Kameyama, Tohoku University

pp. 382

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Session 15b: Clones and Asynchronous Machines

Rigidity Problem of Autodual Clones (Abstract)

Masahiro Miyakawa, Tsukuba College of Technology

Ivo G. Rosenberg, Universit? de Montr?al

pp. 391

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On the Intersection of Maximal Partial Clones and the Join of Minimal Partial Clones (Abstract)

pp. 396

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Logic Synthesis of Controllers for B-Ternary Asynchronous Systems (Abstract)

Yasunori Nagata, University of the Ryukyus

D. Michael Miller, University of Victoria

Masao Mukaidono, Meiji University

pp. 402

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Session 16: Invited Address

Silicon Single-Electron Devices and Their Applications (Abstract)

Yasuo Takahashi, NTT Basic Research Laboratories

Akira Fujiwara, NTT Basic Research Laboratories

Yukinori Ono, NTT Basic Research Laboratories

Katsumi Murase, NTT Basic Research Laboratories

pp. 411

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Session 17a: Arithmetics and Systems

DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage (Abstract)

Takahiro Hanyu, Tohoku University

Hiromitsu Kimura, Tohoku University

Michitaka Kameyama, Tohoku University

pp. 423

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An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access (Abstract)

Yasushi Yuminaka, Gunma University

Osamu Katoh, Gunma University

Yoshisato Sasaki, Gunma University

Takafumi Aoki, Gunma University

Tatsuo Higuchi, Gunma University

pp. 430

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Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic (Abstract)

Shunichi Kaeriyama, Tohoku University

Takahiro Hanyu, Tohoku University

Michitaka Kameyama, Tohoku University

pp. 438

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Session 17b: Verification and Power Estimation

A Method for Approximate Equivalence Checking (Abstract)

Mitch Thornton, Mississippi State University

Rolf Drechsler, Albert-Ludwigs University

Wolfgang Guenther, Albert-Ludwigs University

pp. 447

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Propagation Algorithm of Behavior Probability in Power Estimation Based on Multiple-Valued Logic (Abstract)

Xunwei Wu, Ningbo University

Massoud Pedram, University of Southern California

pp. 453

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Probabilistic Verification of Multiple-Valued Functions (Abstract)

Elena Dubrova, Royal Institute of Technology

Harald Sack, Universit?t Trier

pp. 460

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Author Index (PDF)

pp. 467