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1998
The 28th International Symposium on Multiple-Valued Logic
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The 28th International Symposium on Multiple-Valued Logic
Fukuoka, Japan
May 27-May 29
ISBN: 0-8186-8371-6
Table of Contents
Message from the Symposium Chair
(PDF)
pp. xi
ABSTRACT
PDF
Message from the Program Chair
(PDF)
pp. xii
ABSTRACT
PDF
Symposium Committee
(PDF)
pp. xiii
ABSTRACT
PDF
Organizing Committee
(PDF)
pp. xv
ABSTRACT
PDF
Referees
(PDF)
pp. xvi
ABSTRACT
PDF
Session I: Invited Address
Advanced Circuit Technology to Realize Post Giga-bit DRAM
(Abstract)
T. Okuda
pp. 2
ABSTRACT
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Session IIa: Devices
Development of InGaAs-Based Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits
(Abstract)
T. Baba
T. Uemura
pp. 7
ABSTRACT
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Ultrafast Ternary Quantizer using Resonant Tunneling Devices
(Abstract)
T. Itoh
T. Waho
K. Maezawa
M. Yamamoto
pp. 13
ABSTRACT
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A Josephson Ternary Memory Circuit
(Abstract)
M. Morisue
J. Endo
T. Morooka
N. Shimizu
M. Sakamoto
pp. 19
ABSTRACT
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Session IIb: Cellular Array and Fault Tolerance
A Note on Realizing Multiple-Valued Logic Functions using Akers' Cells ? Cell Sizes and Path Lengths
(Abstract)
I. Takanami
pp. 26
ABSTRACT
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Minimization of Exclusive Sums of Multi-Valued Complex Terms for Logic Cell Arrays
(Abstract)
N. Song
M. Perkowski
pp. 32
ABSTRACT
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Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAs
(Abstract)
Y. Nagata
D. Miller
M. Mukaidono
pp. 38
ABSTRACT
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Session IIIa: Decision Diagrams
Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams
(Abstract)
H. Babu
T. Sasao
pp. 45
ABSTRACT
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Implementing a Multiple-Valued Decision Diagram Package
(Abstract)
D. Miller
R. Drechsler
pp. 52
ABSTRACT
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Ternary Decision Diagrams with Inverted Edges and Cofactoring ? An Application to Discrete Neural Networks Synthesis
(Abstract)
L. Macchiarulo
P. Civera
pp. 58
ABSTRACT
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Session IIIb: Algebra 1
The MacLaurin's and Taylor's Series Expansions of the Symbolic Multiple Valued Logic Functions
(Abstract)
H. Chung
S. Pi
S. Rey
pp. 65
ABSTRACT
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A Characterization of r-Valued Functions Monotonic in an Order Based on Regularity
(Abstract)
N. Takagi
A. Hon-nami
K. Nakashima
pp. 71
ABSTRACT
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Some Results on the Decision for Sheffer Functions in Partial K-Valued Logic(II)
(Abstract)
L. Renren
pp. 77
ABSTRACT
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Session IVa: Logic Design 1
On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels
(Abstract)
J. Butler
T. Sasao
pp. 83
ABSTRACT
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Evolutionary Methods in the Design of Quaternery Digital Circuits
(Abstract)
C. Moraga
W. Wang
pp. 89
ABSTRACT
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Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions
(Abstract)
P. Lindgren
R. Drechsler
B. Becker
pp. 95
ABSTRACT
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Session IVb: Logic
Multiple-Valued Logics for Theorem-Proving in First Order Logic with Equality
(Abstract)
R. Bignall
M. Spinks
pp. 102
ABSTRACT
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Compact Propositional G?del Logics
(Abstract)
M. Baaz
R. Zach
pp. 108
ABSTRACT
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Many-Valued and Annotated Modal Logics
(Abstract)
S. Akama
J. Abe
pp. 114
ABSTRACT
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Session V: Invited Address
The FPGA Challenge
(Abstract)
Z. Vranesic
pp. 121
ABSTRACT
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Session VIa: VLSI Circuits 1
Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits
(Abstract)
J. Shen
K. Tanno
O. Ishizuka
Z. Tang
pp. 128
ABSTRACT
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Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic
(Abstract)
T. Hanyu
T. Saito
M. Kameyama
pp. 134
ABSTRACT
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Set-Valued Logic Circuits for Next Generation VLSI Architectures
(Abstract)
T. Aoki
T. Higuchi
pp. 140
ABSTRACT
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Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences
(Abstract)
Y. Yuminaka
Y. Sasaki
T. Aoki
T. Higuchi
pp. 148
ABSTRACT
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Session VIb: Applications of Multiple-Valued Logic
Image Segmentation Based on Kleene Algebra
(Abstract)
Y. Hata
M. Ishikawa
N. Kamiura
pp. 155
ABSTRACT
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Learning with Permutably Homogenous Multiple-Valued Multiple-Threshold Perceptrons
(Abstract)
A. Ngom
C. Reischer
D. Simovici
I. Stojmenovic
pp. 161
ABSTRACT
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An Error Reducing Approach to Machine Learning using Multi-Valued Functional Decomposition
(Abstract)
C. Files
M. Perkowski
pp. 167
ABSTRACT
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Multi-Valued Functional Decomposition as a Machine Learning Method
(Abstract)
C. Files
M. Perkowski
pp. 173
ABSTRACT
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Session VIIa: Logic Design 2
Fast Multi-Polarity Complex Hadamard Transform for Logic Functions
(Abstract)
B. Falkowski
pp. 180
ABSTRACT
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Reed-Muller-Fourier versus Galois Field Representations of Four-Valued Logic Functions
(Abstract)
R. Stankovic
D. Jankovic
C. Moraga
pp. 186
ABSTRACT
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Constructing an MVL Patterned after Boolean Logic using a Practical Approach
(Abstract)
L. Thaden
pp. 192
ABSTRACT
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Session VIIb: Genetic Algorithms in MVL
A Synthesis Method of the Approximate Reasoning Engine by means of Genetic Algorithm
(Abstract)
Y. Yamamoto
pp. 201
ABSTRACT
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Minimization of Multivalued Multithreshold Perceptrons using Genetic Algorithms
(Abstract)
A. Ngom
I. Stojmenovic
Z. Obradovic
pp. 209
ABSTRACT
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Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm
(Abstract)
M. Keim
N. Drechsler
R. Drechsler
B. Becker
pp. 215
ABSTRACT
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Session VIII: Invited Address
A Review of Multiple-Valued Memory Technology
(Abstract)
P. Gulak
pp. 222
ABSTRACT
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Session IXa: Minimization
On Low Cost Realization of Multiple-Valued Logic Functions
(Abstract)
T. Hozumi
O. Kakusho
Y. Hata
pp. 233
ABSTRACT
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Multiple-Valued Logic Minimization using Universal Literals and Cost Tables
(Abstract)
B. Fraser
G. Dueck
pp. 239
ABSTRACT
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A Frontier Algorithm for Optimization of Multiple-Valued Logic Functions
(Abstract)
M. Abd-El-Barr
pp. 245
ABSTRACT
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Session IXb: Algebra 2
e -Bases of Triadic Logic Operations
(Abstract)
G. Pogosyan
T. Nakamura
pp. 251
ABSTRACT
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Functional Entropy and Decision Trees
(Abstract)
V. Cheushev
V. Shmerko
D. Simovici
S. Yanushkevich
pp. 257
ABSTRACT
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Session Xa: VLSI Circuits 2
Look-up Tables (LUTs) for Multiple-Valued, Combinational Logic
(Abstract)
A. Sheikholeslami
R. Yoshimura
P. Gulak
pp. 264
ABSTRACT
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Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI
(Abstract)
T. Hanyu
K. Teranishi
M. Kameyama
pp. 270
ABSTRACT
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Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued Arithmetic Circuits
(Abstract)
S. Wei
K. Shimizu
pp. 276
ABSTRACT
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Reconfigurable Current-Mode Multiple-Valued Residue Arithmetic Circuits
(Abstract)
K. Shimabukuro
C. Zukeran
pp. 282
ABSTRACT
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Session Xb: Theory of Fuzzy Logic
Minimization of Incompletely Specified Regular Ternary Logic Functions and its Application to Fuzzy Switching Functions
(Abstract)
T. Araki
H. Tatsumi
M. Mukaidono
F. Yamamoto
pp. 289
ABSTRACT
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Upper and Lower Bounds on the Number of Fuzzy/c Switching Functions
(Abstract)
H. Tatsumi
T. Araki
M. Mukaidono
S. Tokumasu
pp. 297
ABSTRACT
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On Closure Operators in Fuzzy Deductive Systems and Fuzzy Algebras
(Abstract)
H. Thiele
pp. 304
ABSTRACT
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A Study on Operations in Interval and Paired Probabilities
(Abstract)
Y. Yamauchi
M. Mukaidono
pp. 310
ABSTRACT
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Session XI: Invited Address
Functional-Device-Based VLSI for Intelligent Electronic Systems
(Abstract)
T. Shibata
pp. 317
ABSTRACT
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Session XII: Invited Address
Multiple-Valued Hyperstructures
(Abstract)
I. Rosenberg
pp. 326
ABSTRACT
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Session XIII: Invited Address
A Novel Nonlinear Synapse Neuron Model Guaranteeing a Global Minimum ? Wavelet Neuron
(Abstract)
T. Yamakawa
pp. 335
ABSTRACT
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Session XIVa: Applications of Fuzzy Logic
Data Envelopment Analysis using Fuzzy Concept
(Abstract)
C. Kahraman
E. Tolga
pp. 338
ABSTRACT
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A Proposal and an Application of a Career-Mode Membership Function
(Abstract)
F. Wakui
M. Hirano
pp. 344
ABSTRACT
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Membership Functions in Automatic Harmonization System
(Abstract)
M. Tokumaru
K. Yamashita
N. Muranaka
S. Imanishi
pp. 350
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On Concurrent Tests of Fuzzy Controllers
(Abstract)
N. Kamiura
Y. Hata
K. Yamato
pp. 356
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Session XIVb: Clone Theory
Generating Sets for Clones and Partial Clones
(Abstract)
F. Börner
L. Haddad
pp. 363
ABSTRACT
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On Partial Clones Containing All Idempotent Partial Operations
(Abstract)
J. Fugère
L. Haddad
pp. 369
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Some Continuous Maps on the Space of Clones in Multiple-Valued Logic
(Abstract)
H. Machida
pp. 374
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A Finite Basis of the Set of All Monotone Partial Functions Defined over a Finite Poset
(Abstract)
A. Nozaki
V. Lashkia
pp. 380
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Index of Authors
(PDF)
pp. 383
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