• I
  • ISMVL
  • 1996
  • 26th International Symposium on Multiple-Valued Logic (ISMVL '96)
Advanced Search 
26th International Symposium on Multiple-Valued Logic (ISMVL '96)
Jantiago de Compostela, SPAIN
January 19-January 31
ISBN: 0-8186-7392-3
Table of Contents
Keynote Address I
Session 1A: Logic Design I
R. Drechsler, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 10
Zeljko Zilic, Department of Electrical and Computer Engineering University of Toronto
Zvonko G. Vranesic, Department of Electrical and Computer Engineering University of Toronto
pp. 16
S. Rahardja, Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
B.J. Falkowski, Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
pp. 24
Session 1B: Logic I
A. Di Nola, Istituto di Matematica, Universita di Napoli, Italy
pp. 32
N. Takagi, Dept. Electr. & Inf., Toyama Prefectural Univ., Japan
K. Nakashima, Dept. Electr. & Inf., Toyama Prefectural Univ., Japan
M. Mukaidono, Dept. Electr. & Inf., Toyama Prefectural Univ., Japan
pp. 37
R. J. Bignall, School of Computing and Information Technology Monash University
M. Spinks, School of Computing and Information Technology Monash University
pp. 43
Session 2A: Fault Modeling, Fault Diagnosis
L.J. de Miguel, Dept. of Syst. Eng. & Control, Valladolid Univ., Spain
M. Mediavilla, Dept. of Syst. Eng. & Control, Valladolid Univ., Spain
J.R. Peran, Dept. of Syst. Eng. & Control, Valladolid Univ., Spain
pp. 50
E.V. Dubrova, Department of Computer Science University of Victoria
J.C. Muzio, Department of Computer Science University of Victoria
pp. 56
Session 2B: Devices
T. Waho, NTT LSI Laboratories
K. J. Chen, NTT LSI Laboratories
M. Yamamoto, NTT LSI Laboratories
pp. 68
L.J. Micheel, Wright Lab., US Air Force, Wright-Patterson Air Force Base, OH, USA
H.L. Hartnagel, Wright Lab., US Air Force, Wright-Patterson Air Force Base, OH, USA
pp. 80
K. W. Current, Electrical and Computer Engineering Department
V. G. Oklobdzija, Electrical and Computer Engineering Department
D. Maksimovic, Electrical and Computer Engineering Department
pp. 86
Session 3A: Circuits, Logic Design I
M. Abd-El-Barr, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
M.N. Hasan, Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
pp. 98
Session 3B: Logic II
M. Baaz, Inst. fur Algebra und Diskrete Math., Tech. Univ. Wien, Austria
C.G. Fermuller, Inst. fur Algebra und Diskrete Math., Tech. Univ. Wien, Austria
pp. 136
Special Session: Helena Rasiowa, In Memoriam: Invited Speakers: G. Malinowski, J.M. Font, and T. Sales
T. Sales, Dept. de Llenguatges i Sistemes Inf., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 148
Session 4A: Algebra I
D.A. Simovici, Dept. of Math. & Comput. Sci., Massachusetts Univ., Boston, MA, USA
C. Reischer, Dept. of Math. & Comput. Sci., Massachusetts Univ., Boston, MA, USA
pp. 166
Session 4B: Artificial Intelligence, Reasoning
A. Bugarin, Universidade de Santiago de Compostela
P. Cari F1ena, Universidade de Santiago de Compostela
M.F. Delgado, Universidade de Santiago de Compostela
S. Barro, Universidade de Santiago de Compostela
pp. 172
Salem Benferhat, Universite Paul Sabatier
Didier Dubois, Universite Paul Sabatier
Henri Prade, Universite Paul Sabatier
pp. 184
Keynote Address II
Session 5A: Algebra II
I.G. Rosenberg, Dept. de Math. et de Stat., Montreal Univ., Que., Canada
pp. 203
Session 5B: Soft Computing
Wenjun Wang, University of Dortmund, Dept. C.Sc.
Claudio Moraga, University of Dortmund, Dept. C.Sc.
pp. 216
Session 6A: Circuits, Logic Design II
Hao Tang, Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
H.C. Lin, Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
pp. 230
Session 6B: Decision Diagrams
J.T. Butler, Dept. of Electr. & Comput. Eng., Naval Postgraduate Sch., Monterey, CA, USA
J.L. Nowlin, Dept. of Electr. & Comput. Eng., Naval Postgraduate Sch., Monterey, CA, USA
T. Sasao, Dept. of Electr. & Comput. Eng., Naval Postgraduate Sch., Monterey, CA, USA
pp. 236
D. M. Miller, VLSI Design and Test Group University of Victoria
N. Muranaka, Department of Electronics Kansai University
pp. 242
T. Sasao, Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
J.T. Butler, Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
pp. 248
B.J. Falkowski, Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
S. Rahardja, Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
pp. 255
Session 7A: Algebra III
V.P. Shmerko, Inst. of Comput. Sci., Tech. Univ. Szczecin, Poland
S. Yanushkevich, Inst. of Comput. Sci., Tech. Univ. Szczecin, Poland
V. Levashenko, Inst. of Comput. Sci., Tech. Univ. Szczecin, Poland
I. Bondar, Inst. of Comput. Sci., Tech. Univ. Szczecin, Poland
pp. 267
Session 7B: Logic III
K. Nakashima, Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan
Y. Nakamura, Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan
N. Takagi, Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan
pp. 290
Elena N. Zaitseva, Belarussian State Economic University
Tatyana G. Kalganova, (Belarussian State Universityof Informatics and Radioelectronics, Brovky
Evgeny G. Kochergov, (Institute of Problems of Criminology, Criminalistics and Forensic Expertise, Gvardeyskaya 7, 220035, Minsk, Republic of Belarus
pp. 302
Usage of this product signifies your acceptance of the Terms of Use.