CSDL - Proceedings I

Message from the Program Chair (PDF)

pp. x

Committees (PDF)

pp. xi

Referees (PDF)

pp. xi

Session 1: VLSI

A High-Speed Interconnect Network Using Ternary Logic (Abstract)

J.K. Madsen, Center for Broadband Telecommun., Tech. Univ. Denmark, Lyngby, Denmark

S.I. Long, Center for Broadband Telecommun., Tech. Univ. Denmark, Lyngby, Denmark

pp. 0002

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Wire-Free Computing Circuits Using Optical Wave-Casting (Abstract)

S. Sakurai, Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

T. Aoki, Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

T. Higuchi, Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

pp. 0008

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Redundant Complex Number Systems (Abstract)

Y. Ohi, Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

T. Aoki, Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

T. Higuchi, Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

pp. 0014

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Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices (Abstract)

M. Ryu, Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan

M. Kameyama, Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan

pp. 0020

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Session 2: Logic Design I

Planar Multiple-Valued Decision Diagrams (Abstract)

T. Sasao, Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan

J.T. Butler, Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan

pp. 0028

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Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation (Abstract)

Z. Zilic, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Z.G. Vranesic, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

pp. 0036

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Properties of the Zhang-Watari Transform (Abstract)

R. Oenning, Dept. of Comput. Sci., Dortmund Univ., Germany

C. Moraga, Dept. of Comput. Sci., Dortmund Univ., Germany

pp. 0044

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Session 3: Circuit Design I

Memory Circuits for Multiple-Valued Logic Voltage Signals (Abstract)

K.W. Current, Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

pp. 0052

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From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators (Abstract)

K. Navi, Univ. de Paris-Sud, Orsay, France

D. Etiemble, Univ. de Paris-Sud, Orsay, France

pp. 0058

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Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic (Abstract)

T. Hanyu, Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

A. Mochizuki, Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

M. Kameyama, Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

pp. 0064

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Session 4: Algebra I

The Radii of Sheffer Functions Over E(3) (Abstract)

J. Beckman, Graduate Sch., City Univ. of New York, NY, USA

T.C. Wesselkamper, Graduate Sch., City Univ. of New York, NY, USA

pp. 0072

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Classification of Functions and Enumeration of Bases of Set Logic under Boolean Compositions (Abstract)

A. Ngom, Dept. of Comput. Sci., Ottawa Univ., Ont., Canada

C. Reischer, Dept. of Comput. Sci., Ottawa Univ., Ont., Canada

I. Stojmenovic, Dept. of Comput. Sci., Ottawa Univ., Ont., Canada

pp. 0078

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Completeness Theory for Vector Partial Multiple-Valued Logic Functions (Abstract)

B.A. Romov, New York, NY, USA

pp. 0086

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Session 5: Device-Based Circuit and Testing I

Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems (Abstract)

Xiaowei Deng, Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

T. Hanyu, Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

M. Kameyama, Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

pp. 0092

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Random Pattern Fault Simulation in Multi-Valued Circuits (Abstract)

R. Drechsler, Dept. of Comput. Sci., Frankfurt Univ., Germany

R. Krieger, Dept. of Comput. Sci., Frankfurt Univ., Germany

B. Becker, Dept. of Comput. Sci., Frankfurt Univ., Germany

pp. 0098

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The Evaluation of Full Sensitivity for Test Generation in MVL Circuits (Abstract)

E.V. Dubrova, Dept. of Comput. Sci., Victoria Univ., BC, Canada

D.B. Gurov, Dept. of Comput. Sci., Victoria Univ., BC, Canada

J.C. Muzio, Dept. of Comput. Sci., Victoria Univ., BC, Canada

pp. 0104

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Session 6: Logic I

Paraconsistent Circumscription: First-Order Case (Abstract)

Zuoquan Lin, Comput. Sci. Dept., Shantou Univ., Guangdong, China

pp. 0112

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Novel Quantized Transform for Ternary Systems (Abstract)

B.J. Falkowski, Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore

S. Rahardja, Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore

pp. 0117

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A Three-Valued Semantics for Discourse Representations (Abstract)

S. Akama, Comput. Logic Lab., Teikyo Heisei Univ., Chiba, Japan

Y. Nakayama, Comput. Logic Lab., Teikyo Heisei Univ., Chiba, Japan

pp. 0123

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Invited Address

Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits (Abstract)

T. Waho, NTT LSI Labs., Atsugi, Japan

pp. 0130

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Session 7: Fuzzy Logic

On the Mutual Definability of Fuzzy Tolerance Relations and Fuzzy Tolerance Coverings (Abstract)

H. Thiele, Dept. of Comput. Sci. 1, Dortmund Univ., Germany

pp. 0140

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On Lattice-Isomorphism Between Fuzzy Equivalence Relations and Fuzzy Partitions (Abstract)

N. Schmechel, Dept. of Comput. Sci. 1, Dortmund Univ., Germany

pp. 0146

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Segment Matrix Vector Quantization and Fuzzy Logic for Isolated-Word Speech Recognition (Abstract)

Liusheng Liu, Inst. of Microelectron., Tsinghua Univ., Beijing, China

Zhijian Li, Inst. of Microelectron., Tsinghua Univ., Beijing, China

Bingxue Shi, Inst. of Microelectron., Tsinghua Univ., Beijing, China

pp. 0152

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Session 8: Logic Design II

Efficient Algorithm for the Generation of Fixed Polarity Quaternary Reed-Muller Expansions (Abstract)

B.J. Falkowski, Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore

S. Rahardia, Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore

pp. 0158

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Factorization of Multi-Valued Logic Functions (Abstract)

Hui Min Wang, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Chung Len Lee, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

J.E. Chen, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

pp. 0164

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On Input Permutation Technique for Multiple-Valued Logic Synthesis (Abstract)

Y. Hata, Dept. of Comput. Eng., Himeji Inst. of Technol., Japan

N. Kamiura, Dept. of Comput. Eng., Himeji Inst. of Technol., Japan

K. Yamato, Dept. of Comput. Eng., Himeji Inst. of Technol., Japan

pp. 0170

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Session 9: Device-Based Circuit and Testing II

The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors (Abstract)

Wang Shoujue, Inst. of Semicond., Acad. Sinica, Beijing, China

Wu Xunwei, Inst. of Semicond., Acad. Sinica, Beijing, China

Feng Hongjuan, Inst. of Semicond., Acad. Sinica, Beijing, China

pp. 0178

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A Fuzzy Membership Function Circuit Using Hysteretic Resonant Tunneling Diodes (Abstract)

Hao Tang, Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA

Hung Chang Lin, Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA

pp. 0182

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On Designing of 4-Valued Memory with Double-Gate TFT (Abstract)

Chung Len Lee, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Horng Nan Chern, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Min Shung Liao, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Hui Min Wang, Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

pp. 0187

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Session 10: Algebra II

Join-Irreducible Clones of Multiple-Valued Logic Algebra (Abstract)

G. Pogosyan, Div. of Natural Sciences, Int. Christian Univ., Tokyo, Japan

A. Nozaki, Div. of Natural Sciences, Int. Christian Univ., Tokyo, Japan

pp. 0194

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Finitary Approximations and Metric Structure of the Space of Clones (Abstract)

H. Machida, Dept. of Math., Hitotsubashi Univ., Tokyo, Japan

pp. 0200

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Finite Algebraic Models for Residuated Logic (Abstract)

W. MacCaull, Dept. of Math. & Comput. Sci., St. Francis Xavier Univ., Antigonish, NS, Canada

pp. 0206

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Session 11: Circuit Design II

Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm (Abstract)

A.K. Jain, Canadian Microelectron. Corp., Queen's Univ., Kingston, Ont., Canada

M.H. Abd-El-Barr, Canadian Microelectron. Corp., Queen's Univ., Kingston, Ont., Canada

R.J. Bolton, Canadian Microelectron. Corp., Queen's Univ., Kingston, Ont., Canada

pp. 0216

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Race-Hazard and Skip-Hazard in Multivalued Combinational Circuits (Abstract)

Xunwei Wu, Dept. of Electron. Eng., Hangzhou Univ., China

Xiexiong Chen, Dept. of Electron. Eng., Hangzhou Univ., China

Jizhong Shen, Dept. of Electron. Eng., Hangzhou Univ., China

pp. 0222

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2^k-ary Cyclic AN Codes for Burst Error Correction (Abstract)

R. Murakami, Fac. of Eng., Tokushima Univ., Japan

Y. Ohkura, Fac. of Eng., Tokushima Univ., Japan

R. Shimada, Fac. of Eng., Tokushima Univ., Japan

pp. 0228

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Session 12: Logic II

A Characterization of Kleenean Functions (Abstract)

N. Takagi, Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan

K. Nakashima, Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan

H. Kikuchi, Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan

M. Mukaidono, Dept. of Electron. & Inf., Toyama Prefectural Univ., Japan

pp. 0236

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Uniqueness of Partially Specified Multiple-Valued Kleenean Function (Abstract)

H. Kikuchi, Dept. of Electr. Eng., Tokai Univ., Hiratsuka, Japan

S. Nakanishi, Dept. of Electr. Eng., Tokai Univ., Hiratsuka, Japan

N. Takagi, Dept. of Electr. Eng., Tokai Univ., Hiratsuka, Japan

M. Mukaidono, Dept. of Electr. Eng., Tokai Univ., Hiratsuka, Japan

pp. 0242

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On Logic of Paradox (Abstract)

Zuoquan Lin, Comput. Sci. Dept., Shantou Univ., China

Wei Li, Comput. Sci. Dept., Shantou Univ., China

pp. 0248

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Decomposition of Multiple-Valued Functions (Abstract)

T. Luba, Inst. of Telecommun., Warsaw Univ. of Technol., Poland

pp. 0256

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Session 13: Artificial Intelligence

Some New Results for Multiple-Valued Genetic Algorithms (Abstract)

T.C. Wesselkamper, Graduate Sch., City Univ. of New York, NY, USA

J. Danowitz, Graduate Sch., City Univ. of New York, NY, USA

pp. 0264

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Learning Multiple-Valued Logic Networks Based on Back Propagation (Abstract)

Zheng Tang, Fac. of Eng., Miyazaki Univ., Japan

O. Ishizuka, Fac. of Eng., Miyazaki Univ., Japan

K. Tanno, Fac. of Eng., Miyazaki Univ., Japan

pp. 0270

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Three-Valued Constructive Logic and Logic Programs (Abstract)

S. Akama, Dept. of Inf. Syst., Teikyo Heisei Univ., Chiba, Japan

pp. 0276

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Session 14: Logic Design III

Functional Decision Diagrams for Multiple-Valued Functions (Abstract)

R.S. Stankovic, Brace Taskovica 17/29, Nis, Yugoslavia

pp. 0284

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Multiple-Valued Logic Design Using Multiple-Valued EXOR (Abstract)

A. Hozumi, Fac. of Eng., Himeji Inst. of Technol., Japan

N. Kamiura, Fac. of Eng., Himeji Inst. of Technol., Japan

Y. Hata, Fac. of Eng., Himeji Inst. of Technol., Japan

K. Yamato, Fac. of Eng., Himeji Inst. of Technol., Japan

pp. 0290

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Author Index (PDF)

pp. 0296