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Eighth IEEE International Symposium on Multimedia (ISM'06)
Multiprocessing Template for Media Applications
San Diego, CA
December 11-December 13
ISBN: 0-7695-2746-9
Jeroen Leijten, Silicon Hive
Menno Lindwer, Silicon Hive
Within SoCs for embedded media applications, performance and computational efficiency can only grow through scalability, dedicated instructions, and specialized memory sub-systems. Scalability can only be achieved through short wires and low fan-in and fanout. The presented multi-processor template makes use of these properties. It provides multiple threads of control (cell-level multi processing), each processor cell having a multitude of issue slots, localised register files, memories, and interconnects. The template allows the compiler to control all of these resources separately, eliminating hardware overhead for instruction decoding, pipeline control, hazard detection, and bypass networks. The template also integrates media-oriented and SIMD instructions, which the compiler can automatically select. This paper describes the template underlying several multimedia multi-processor designs.
Citation:
Jeroen Leijten, Menno Lindwer, "Multiprocessing Template for Media Applications," ism, pp.475-480, Eighth IEEE International Symposium on Multimedia (ISM'06), 2006
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