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2010 International Symposium on Electronic System Design
Power Reduction in Embedded System on FPGA Using on the Fly Partial Reconfiguration
Bhubaneswar, Orissa India
December 20-December 22
ISBN: 978-0-7695-4294-2
The realm of embedded systems is quite large and is predominantly carried out around the general purpose processor and microcontrollers. The present-day FPGA provides a platform that supports both processor and custom logic requirements. econfigurable technologies provide designers the opportunity to diminish the life-cycle into processor creation. New emerging capabilities in Field Programmable Gate Array (FPGA), including improvements in time delays, and cost per unit device, are enabling-us to incorporate these devices in several designs as reconfigurable embedded processors. New Electronic-Design-Automation (EDA) tools, allow us to construct rapid prototypes of Systems-on-a-Chip in a very mature way. The design is realized into hardware-software co-design environments, and the use of soft-cores like processor and peripherals reduces drastically the development cycle. Till date microcontrollers have an edge over the FPGA in terms of power. In order to enable use of FPGA in low power-embedded system a novel method of power management using on the fly partial reconfiguration is demonstrated in this paper. considerable amount of power saving is observed and presented here.
Index Terms:
System on programmable chip, difference based partial reconfiguration, Power management in FPGA
Citation:
Sheetal U. Bhandari, Shaila Subbaraman, Shashank Pujari, "Power Reduction in Embedded System on FPGA Using on the Fly Partial Reconfiguration," ised, pp.77-80, 2010 International Symposium on Electronic System Design, 2010
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