CSDL - Proceedings I

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

Title Page iv - Copyright Page (PDF)

pp. iv

Table of Contents (PDF)

pp. v-ix

Message from the General Chairs (PDF)

pp. x

Message from the Program Chair (PDF)

pp. xi

Officers (PDF)

pp. xii-xiv

Reviewers (PDF)

pp. xv-xviii

ISCA-35 Sponsors (PDF)

pp. xix

Achieving Out-of-Order Performance with Almost In-Order Complexity (Abstract)

Francis Tseng

Yale N. Patt

pp. 3-12

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Fetch-Criticality Reduction through Control Independence (Abstract)

pp. 13-24

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A Two-Level Load/Store Queue Based on Execution Locality (Abstract)

pp. 25-36

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Self-Optimizing Memory Controllers: A Reinforcement Learning Approach (Abstract)

pp. 39-50

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A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies (Abstract)

pp. 51-62

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Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (Abstract)

Onur Mutlu

Thomas Moscibroda

pp. 63-74

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Technology-Driven, Highly-Scalable Dragonfly Topology (Abstract)

pp. 77-88

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Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks (Abstract)

pp. 89-100

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Polymorphic On-Chip Networks (Abstract)

pp. 101-112

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Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory (Abstract)

pp. 115-126

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TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory (Abstract)

pp. 127-138

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Flexible Decoupled Transactional Memory Support (Abstract)

pp. 139-150

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Corona: System Implications of Emerging Nanophotonic Technology (Abstract)

Raymond G. Beausoleil

Jung Ho Ahn

pp. 153-164

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Microcoded Architectures for Ion-Tap Quantum Computers (Abstract)

Lucas Kreger-Stickles

Mark Oskin

pp. 165-176

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Running a Quantum Circuit at the Speed of Data (Abstract)

pp. 177-188

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ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency (Abstract)

pp. 191-202

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Trading off Cache Capacity for Reliability to Enable Low Voltage Operation (Abstract)

pp. 203-214

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Counting Dependence Predictors (Abstract)

pp. 215-226

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Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support (Abstract)

Natalie Enright Jerger

Li-Shiuan Peh

Mikko Lipasti

pp. 229-240

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iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures (Abstract)

pp. 241-250

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MIRA: A Multi-layered On-Chip Interconnect Router Architecture (Abstract)

pp. 251-261

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Rerun: Exploiting Episodes for Lightweight Memory Race Recording (Abstract)

Derek R. Hower

Mark D. Hill

pp. 265-276

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Atom-Aid: Detecting and Surviving Atomicity Violations (Abstract)

pp. 277-288

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DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Ef?ciently (Abstract)

pp. 289-300

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Intra-disk Parallelism: An Idea Whose Time Has Come (Abstract)

pp. 303-314

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Parthasarathy Ranganathan

Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments (Abstract)

Kevin Lim

pp. 315-326

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Improving NAND Flash Based Disk Caches (Abstract)

pp. 327-338

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Online Estimation of Architectural Vulnerability Factor for Soft Errors (Abstract)

pp. 341-352

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A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime (Abstract)

pp. 353-362

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Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors (Abstract)

Radu Teodorescu

Josep Torrellas

pp. 363-374

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Flexible Hardware Acceleration for Instruction-Grain Program Monitoring (Abstract)

pp. 377-388

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VEAL: Virtualized Execution Accelerator for Loops (Abstract)

pp. 389-400

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From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware (Abstract)

Xi Wu

pp. 401-412

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Software-Controlled Priority Characterization of POWER5 Processor (Abstract)

pp. 415-426

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Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction (Abstract)

pp. 427-438

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Atomic Vector Operations on Chip Multiprocessors (Abstract)

Christopher J. Hughes

pp. 441-452

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3D-Stacked Memory Architectures for Multi-core Processors (Abstract)

Gabriel H. Loh

pp. 453-464

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Author Index (PDF)

pp. 465-466

Publisher's Information (PDF)

pp. 468