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33rd International Symposium on Computer Architecture (ISCA'06)
Boston, Massachusetts
June 17-June 21
ISBN: 0-7695-2608-X
Table of Contents
Introduction
Keynote 2
Keynote 1
Keynote 3
Session 1: Interconnection Networks
Steve Scott, Cray Inc., Chippewa Falls,Wisconsin
Dennis Abts, Cray Inc., Chippewa Falls,Wisconsin
John Kim, Stanford University
William J. Dally, Stanford University
pp. 16-28
Session 2: Memory Models
Christoph von Praun, IBM T.J. Watson Research Center, Yorktown Heights, NY
Harold W. Cain, IBM T.J. Watson Research Center, Yorktown Heights, NY
Jong-Deok Choi, IBM T.J. Watson Research Center, Yorktown Heights, NY
Kyung Dong Ryu, IBM T.J. Watson Research Center, Yorktown Heights, NY
pp. 41-52
Austen McDonald, Stanford University
JaeWoong Chung, Stanford University
Brian D. Carlstrom, Stanford University
Chi Cao Minh, Stanford University
Hassan Chafi, Stanford University
Christos Kozyrakis, Stanford University
Kunle Olukotun, Stanford University
pp. 53-65
Session 3: Power and Thermal Management
Yuan Lin, University of Michigan at Ann Arbor
Hyunseok Lee, University of Michigan at Ann Arbor
Mark Woh, University of Michigan at Ann Arbor
Yoav Harel, University of Michigan at Ann Arbor
Scott Mahlke, University of Michigan at Ann Arbor
Trevor Mudge, University of Michigan at Ann Arbor
Chaitali Chakrabarti, Arizona State University
Krisztian Flautner, ARM, Ltd.n Cambridge,UK
pp. 89-101
Session 4: Multicore
Weidong Shi, Georgia Institute of Technology
Hsien-Hsin S. Lee, Georgia Institute of Technology
Laura `Falk, University of Michigan, Ann Arbor
Mrinmoy Ghosh, Georgia Institute of Technology
pp. 102-113
Richard A. Hankins, Microarchitecture Research Lab, Intel Corporation
Gautham N. Chinya, Microarchitecture Research Lab, Intel Corporation
Jamison D. Collins, Microarchitecture Research Lab, Intel Corporation
Perry H. Wang, Microarchitecture Research Lab, Intel Corporation
Ryan Rakvic, Microarchitecture Research Lab, Intel Corporation
Hong Wang, Microarchitecture Research Lab, Intel Corporation
John P. Shen, Microarchitecture Research Lab, Intel Corporation
pp. 114-127
Session 5A: Memory Access Issues
Feihui Li, Pennsylvania State University
Chrysostomos Nicopoulos, Pennsylvania State University
Thomas Richardson, Pennsylvania State University
Yuan Xie, Pennsylvania State University
Vijaykrishnan Narayanan, Pennsylvania State University
Mahmut Kandemir, Pennsylvania State University
pp. 130-141
Session 5B: Cache Design I
Moinuddin K. Qureshi, University of Texas at Austin
Daniel N. Lynch, University of Texas at Austin
Onur Mutlu, University of Texas at Austin
Yale N. Patt, University of Texas at Austin
pp. 167-178
Session 6A: Security and Network Processors
Chenyu Yan, Georgia Institute of Technology
Daniel Englender, Georgia Institute of Technology
Milos Prvulovic, Georgia Institute of Technology
Brian Rogers, North Carolina State University
Yan Solihin, North Carolina State University
pp. 179-190
Jahangir Hasan, Purdue University, West Lafayette, IN
Srihari Cadambi, NEC Laboratories America Inc., Princeton, NJ
Venkatta Jakkula, NEC Laboratories America Inc., Princeton, NJ
Srimat Chakradhar, NEC Laboratories America Inc., Princeton, NJ
pp. 203-215
Session 6B: Multithreading
Luis Ceze, University of Illinois at Urbana-Champaign
James Tuck, University of Illinois at Urbana-Champaign
Josep Torrellas, University of Illinois at Urbana-Champaign
Calin Cascaval, IBM T.J. Watson Research Center
pp. 227-238
Session 7A: Cache Design II
Stephen Somogyi, Carnegie Mellon University
Thomas F. Wenisch, Carnegie Mellon University
Anastassia Ailamaki, Carnegie Mellon University
Babak Falsafi, Carnegie Mellon University
Andreas Moshovos, University of Toronto
pp. 252-263
Jichuan Chang, University of Wisconsin-Madison
Gurindar S. Sohi, University of Wisconsin-Madison
pp. 264-276
Session 7B: Potpourri
Qing Yang, University of Rhode Island
Weijun Xiao, University of Rhode Island
Jin Ren, University of Rhode Island
pp. 289-301
Session 8A: Dataflow
Steven Swanson, University of Washington
Andrew Putnam, University of Washington
Martha Mercaldi, University of Washington
Martha Mercaldi, University of Washington
Ken Michelson, University of Washington
Andrew Petersen, University of Washington
Andrew Schwerin, University of Washington
Mark Oskin, University of Washington
Susan J. Eggers, University of Washington
pp. 314-326
Session 8B: Cache Coherence
Karin Strauss, University of Illinois, Urbana-Champaign
Xiaowei Shen, IBM T. J. Watson Research Center
Josep Torrellas, University of Illinois, Urbana-Champaign
pp. 327-338
Session 9: Quantum Computing
Rodney Van Meter, Keio University and CREST-JST
Kae Nemoto, National Institute of Informatics, Japan
W. J. Munro, Hewlett-Packard Laboratories, UK
Kohei M. Itoh, Keio University and CREST-JST
pp. 354-365
Nemanja Isailovic, University of California, Berkeley
Yatish Patel, University of California, Berkeley
Mark Whitney, University of California, Berkeley
John Kubiatowicz, University of California, Berkeley
pp. 366-377
Darshan D. Thaker, University of California at Davis
Tzvetan S. Metodi, University of California at Davis
Andrew W. Cross, Massachusetts Institute of Technology
Isaac L. Chuang, Massachusetts Institute of Technology
Frederic T. Chong, University of California at Santa Barbara
pp. 378-390
Author Index
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