CSDL - Proceedings I

Program Chair?s Message (PDF)

pp. x-xv

Committees (PDF)

pp. xvi

Reviewers (PDF)

pp. xvii-xviii

Session 1: Security

Architecture for Protecting Critical Secrets in Microprocessors (Abstract)

Ruby B. Lee, Princeton University

Peter C. S. Kwan, Princeton University

John P. McGregor, Princeton University

Jeffrey Dwoskin, Princeton University

Zhenghong Wang, Princeton University

pp. 2-13

PDF

High Efficiency Counter Mode Security Architecture via Prediction and Precomputation (Abstract)

Weidong Shi, Georgia Institute of Technology

Hsien-Hsin S. Lee, Georgia Institute of Technology

Mrinmoy Ghosh, Georgia Institute of Technology

Chenghuai Lu, Georgia Institute of Technology

Alexandra Boldyreva, Georgia Institute of Technology

pp. 14-24

PDF

Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions (Abstract)

G. Edward Suh, Massachusetts Institute of Technology

Charles W. O?Donnell, Massachusetts Institute of Technology

Ishan Sachdev, Massachusetts Institute of Technology

Srinivas Devadas, Massachusetts Institute of Technology

pp. 25-36

PDF

Session 2a: Interacting with Disks and Networks

Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal Management (Abstract)

Sudhanva Gurumurthi, Pennsylvania State University

Anand Sivasubramaniam, Pennsylvania State University

Vivek K. Natarajan, Pennsylvania State University

pp. 38-49

PDF

Direct Cache Access for High Bandwidth Network I/O (Abstract)

Ram Huggahalli, Intel Corporation

Ravi Iyer, Intel Corporation

Scott Tetrick, Intel Corporation

pp. 50-59

PDF

Deconstructing Commodity Storage Clusters (Abstract)

Haryadi S. Gunawi, University of Wisconsin - Madison

Nitin Agrawal, University of Wisconsin - Madison

Andrea C. Arpaci-Dusseau, University of Wisconsin - Madison

Remzi H. Arpaci-Dusseau, University of Wisconsin - Madison

Jiri Schindler, EMC Corporation

pp. 60-71

PDF

Session 2b: Memory Compression and Renamer Optimizations

A Robust Main-Memory Compression Scheme (Abstract)

pp. 74-85

PDF

Continuous Optimization (Abstract)

pp. 86-97

PDF

RENO — A Rename-Based Instruction Optimizer (Abstract)

pp. 98-109

PDF

Session 3a: Specialized Processors

A High Throughput String Matching Architecture for Intrusion Detection and Prevention (Abstract)

Lin Tan, University of California at Santa Barbara

Timothy Sherwood, University of California at Santa Barbara

pp. 112-122

PDF

A Tree Based Router Search Engine Architecture with Single Port Memories (Abstract)

Florin Baboescu, University of California at San Diego

Dean M. Tullsen, University of California at San Diego

Grigore Rosu, University of Illinois at Urbana-Champaign

Sumeet Singh, University of California at San Diego

pp. 123-133

PDF

An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems (Abstract)

Shorin Kyo, NEC Corporation

Shin?ichiro Okazaki, NEC Corporation

Tamio Arai, University of Tokyo

pp. 134-145

PDF

Session 3b: Detecting Faults

Design and Evaluation of Hybrid Fault-Detection Systems (Abstract)

George A. Reis, Princeton University

Jonathan Chang, Princeton University

Neil Vachharajani, Princeton University

Ram Rangan, Princeton University

David I. August, Princeton University

Shubhendu S. Mukherjee, Intel Massachusetts

pp. 148-159

PDF

Rescue: A Microarchitecture for Testability and Defect Tolerance (Abstract)

Ethan Schuchman, Purdue University

T. N. Vijaykumar, Purdue University

pp. 160-171

PDF

Opportunistic Transient-Fault Detection (Abstract)

Mohamed A. Gomaa, Purdue University

T. N. Vijaykumar, Purdue University

pp. 172-183

PDF

Session 4a: Quantum Computing and Very Low Power

An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures (Abstract)

Steven Balensiefer, University of Washington

Lucas Kregor-Stickles, University of Washington

Mark Oskin, University of Washington

pp. 186-196

PDF

Energy Optimization of Subthreshold-Voltage Sensor Network Processors (Abstract)

Leyla Nazhandali, University of Michigan

Bo Zhai, University of Michigan

Javin Olson, University of Michigan

Anna Reeves, University of Michigan

Michael Minuth, University of Michigan

Ryan Helfand, University of Michigan

Sanjay Pant, University of Michigan

Todd Austin, University of Michigan

David Blaauw, University of Michigan

pp. 197-207

PDF

An Ultra Low Power System Architecture for Sensor Network Applications (Abstract)

Mark Hempstead, Harvard University

Nikhil Tripathi, Harvard University

Patrick Mauro, Harvard University

Gu-Yeon Wei, Harvard University

David Brooks, Harvard University

pp. 208-219

PDF

Session 4b: Coherence

Temporal Streaming of Shared Memory (Abstract)

Thomas F. Wenisch, Carnegie Mellon University

Stephen Somogyi, Carnegie Mellon University

Nikolaos Hardavellas, Carnegie Mellon University

Jangwoo Kim, Carnegie Mellon University

Anastassia Ailamaki, Carnegie Mellon University

Babak Falsafi, Carnegie Mellon University

pp. 222-233

PDF

RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence (Abstract)

Andreas Moshovos, Univerisity of Toronto

pp. 234-245

PDF

Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking (Abstract)

Jason F. Cantin, University of Wisconsin - Madison

Mikko H. Lipasti, University of Wisconsin - Madison

James E. Smith, University of Wisconsin - Madison

pp. 246-257

PDF

Session 5a: Applying Compilers and Debugging Support

Improving Program Efficiency by Packing Instructions into Registers (Abstract)

Stephen Hines, Florida State University

Joshua Green, Florida State University

Gary Tyson, Florida State University

David Whalley, Florida State University

pp. 260-271

PDF

An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors (Abstract)

Nathan Clark, University of Michigan - Ann Arbor

Jason Blome, University of Michigan - Ann Arbor

Michael Chu, University of Michigan - Ann Arbor

Scott Mahlke, University of Michigan - Ann Arbor

Stuart Biles, ARM, Ltd.

Kriszti? Flautner, ARM, Ltd.

pp. 272-283

PDF

BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging (Abstract)

Satish Narayanasamy, University of California at San Diego

Gilles Pokam, University of California at San Diego

Brad Calder, University of California at San Diego

pp. 284-295

PDF

Session 5b: Power

Mitigating Amdahl?s Law through EPI Throttling (Abstract)

Murali Annavaram, Intel Corporation

Ed Grochowski, Intel Corporation

John Shen, Intel Corporation

pp. 298-309

PDF

Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines (Abstract)

Emil Talpes, Carnegie Mellon University

Diana Marculescu, Carnegie Mellon University

pp. 310-321

PDF

Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection (Abstract)

Vlad Petric, University of Pennsylvania

Amir Roth, University of Pennsylvania

pp. 322-333

PDF

Session 6a: Chip Multiprocessor Memory Hierarchies

Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors (Abstract)

Michael Zhang, Massachusetts Institute of Technology

Krste Asanović, Massachusetts Institute of Technology

pp. 336-345

PDF

Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors (Abstract)

Evan Speight, IBM Research

Hazim Shafi, IBM Research

Lixin Zhang, IBM Research

Ram Rajamony, IBM Research

pp. 346-356

PDF

Optimizing Replication, Communication, and Capacity Allocation in CMPs (Abstract)

Zeshan Chishti, Purdue University

Michael D. Powell, Purdue University

T. N. Vijaykumar, Purdue University

pp. 357-368

PDF

Session 6b: Runahead and Branch Prediction

Techniques for Efficient Processing in Runahead Execution Engines (Abstract)

Onur Mutlu, University of Texas at Austin

Hyesoon Kim, University of Texas at Austin

Yale N. Patt, University of Texas at Austin

pp. 370-381

PDF

Piecewise Linear Branch Prediction (Abstract)

Daniel A. Jiménez, Rutgers University

pp. 382-393

PDF

Analysis of the O-GEometric History Length Branch Predictor (Abstract)

André Seznec, IRISA/INRIA/HIPEAC

pp. 394-405

PDF

Session 7a: Interconnection Networks

Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling (Abstract)

Rakesh Kumar, University of California at San Diego

Victor Zyuban, IBM TJ Watson Research Center

Dean M. Tullsen, University of California at San Diego

pp. 408-419

PDF

Microarchitecture of a High-Radix Router (Abstract)

John Kim, Stanford University

William J. Dally, Stanford University

Brian Towles, D.E. Shaw Research and Development

Amit K. Gupta, Stanford University

pp. 420-431

PDF

Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks (Abstract)

Daeho Seo, Purdue University

Akif Ali, Purdue University

Won-Taek Lim, Purdue University

Nauman Rafique, Purdue University

Mithuna Thottethodi, Purdue University

pp. 432-443

PDF

Session 7b: Load and Store Queues

Scalable Load and Store Processing in Latency Tolerant Processors (Abstract)

Amit Gandhi, Portland State University

Haitham Akkary, Intel Corporation

Ravi Rajwar, Intel Corporation

Srikanth T. Srinivasan, Intel Corporation

Konrad Lai, Intel Corporation

pp. 446-457

PDF

Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization (Abstract)

Amir Roth, University of Pennsylvania

pp. 458-468

PDF

Store Buffer Design in First-Level Multibanked Data Caches (Abstract)

E. F. Torres, University de Zaragoza

P. Iba?, University de Zaragoza

V. Vi?als, University de Zaragoza

J. M. Llaber?, University Polit?cnica de Catalunya

pp. 469-480

PDF

Session 8a: Multiprocessor Issues

Dynamic Verification of Sequential Consistency (Abstract)

Albert Meixner, Duke University

Daniel J. Sorin, Duke University

pp. 482-493

PDF

Virtualizing Transactional Memory (Abstract)

Ravi Rajwar, Intel Corporation

Maurice Herlihy, Brown University

Konrad Lai, Intel Corporation

pp. 494-505

PDF

The Impact of Performance Asymmetry in Emerging Multicore Architectures (Abstract)

Saisanthosh Balakrishnan, University of Wisconsin-Madison

Ravi Rajwar, Intel Corporation

Mike Upton, Intel Corporation

Konrad Lai, Intel Corporation

pp. 506-517

PDF

Session 8b: Reliability and a Cache Organization

Exploiting Structural Duplication for Lifetime Reliability Enhancement (Abstract)

Jayanth Srinivasan, University of Illinois at Urbana-Champaign

Sarita V. Adve, University of Illinois at Urbana-Champaign

Pradip Bose, IBM T.J. Watson Research Center

Jude A. Rivers, IBM T.J. Watson Research Center

pp. 520-531

PDF

Computing Architectural Vulnerability Factors for Address-Based Structures (Abstract)

Arijit Biswas, Intel Corp.

Paul Racunas, Intel Corp.

Razvan Cheveresan, Sun Microsystems

Joel Emer, Intel Corp.

Shubhendu S. Mukherjee, Intel Corp.

Ram Rangan, Princeton University

pp. 532-543

PDF

The V-Way Cache: Demand Based Associativity via Global Replacement (Abstract)

Moinuddin K. Qureshi, University of Texas at Austin

David Thompson, University of Texas at Austin

Yale N. Patt, University of Texas at Austin

pp. 544-555

PDF

Author Index

Author Index (PDF)

pp. 556-557