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32nd Annual International Symposium on Computer Architecture (ISCA'05)
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions
Madison, Wisconsin
June 04-June 08
ISBN: 0-7695-2270-X
G. Edward Suh, Massachusetts Institute of Technology
Charles W. O?Donnell, Massachusetts Institute of Technology
Ishan Sachdev, Massachusetts Institute of Technology
Srinivas Devadas, Massachusetts Institute of Technology
Secure processors enable new applications by ensuring private and authentic program execution even in the face of physical attack. In this paper we present the AEGIS secure processor architecture, and evaluate its RTL implementation on FPGAs. By using Physical Random Functions, we propose a new way of reliably protecting and sharing secrets that is more secure than existing solutions based on non-volatile memory. Our architecture gives applications the flexibility of trusting and protecting only a portion of a given process, unlike prior proposals which require a process to be protected in entirety. We also put forward a specific model of how secure applications can be programmed in a high-level language and compiled to run on our system. Finally, we evaluate a fully functional FPGA implementation of our processor, assess the implementation tradeoffs, compare performance, and demonstrate the benefits of partially protecting a program.
Citation:
G. Edward Suh, Charles W. O?Donnell, Ishan Sachdev, Srinivas Devadas, "Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions," isca, pp.25-36, 32nd Annual International Symposium on Computer Architecture (ISCA'05), 2005
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